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[123.204.46.122]) by smtp.gmail.com with ESMTPSA id r24sm15671364pfh.69.2019.10.07.20.46.38 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 07 Oct 2019 20:46:40 -0700 (PDT) From: Jian-Hong Pan To: Bjorn Helgaas , Matthew Wilcox Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, linux-nvme@lists.infradead.org, linux@endlesssm.com, Jian-Hong Pan Subject: [PATCH] PCI/MSI: Fix restoring of MSI-X vector control's mask bit Date: Tue, 8 Oct 2019 11:42:39 +0800 Message-Id: <20191008034238.2503-1-jian-hong@endlessm.com> X-Mailer: git-send-email 2.23.0 MIME-Version: 1.0 Sender: linux-pci-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-pci@vger.kernel.org MSI-X vector control's bit 0 is the mask bit, which masks the corresponding interrupt request, or not. Other reserved bits might be used for other purpose by device vendors. For example, the values of Kingston NVMe SSD's MSI-X vector control are neither 0, nor 1, but other values [1]. The original restoring logic in system resuming uses the whole MSI-X vector control value as the flag to set/clear the mask bit. However, this logic conflicts the idea mentioned above. It may mislead system to disable the MSI-X vector entries. That makes system get no interrupt from Kingston NVMe SSD after resume and usually get NVMe I/O timeout error. [ 174.715534] nvme nvme0: I/O 978 QID 3 timeout, completion polled This patch takes only the mask bit of original MSI-X vector control value as the flag to fix this issue. [1] https://bugzilla.kernel.org/show_bug.cgi?id=204887#c8 Buglink: https://bugzilla.kernel.org/show_bug.cgi?id=204887 Fixed: f2440d9acbe8 ("PCI MSI: Refactor interrupt masking code") Signed-off-by: Jian-Hong Pan --- drivers/pci/msi.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-) diff --git a/drivers/pci/msi.c b/drivers/pci/msi.c index 0884bedcfc7a..deae3d5acaf6 100644 --- a/drivers/pci/msi.c +++ b/drivers/pci/msi.c @@ -433,6 +433,7 @@ static void __pci_restore_msi_state(struct pci_dev *dev) static void __pci_restore_msix_state(struct pci_dev *dev) { struct msi_desc *entry; + u32 flag; if (!dev->msix_enabled) return; @@ -444,8 +445,10 @@ static void __pci_restore_msix_state(struct pci_dev *dev) PCI_MSIX_FLAGS_ENABLE | PCI_MSIX_FLAGS_MASKALL); arch_restore_msi_irqs(dev); - for_each_pci_msi_entry(entry, dev) - msix_mask_irq(entry, entry->masked); + for_each_pci_msi_entry(entry, dev) { + flag = entry->masked & PCI_MSIX_ENTRY_CTRL_MASKBIT; + msix_mask_irq(entry, flag); + } pci_msix_clear_and_set_ctrl(dev, PCI_MSIX_FLAGS_MASKALL, 0); }