| Message ID | 20190719210326.15466-5-richard.henderson@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | target/arm: Implement ARMv8.1-VHE | expand |
Richard Henderson <richard.henderson@linaro.org> writes: > This is less complex than the LPAE case, but still we now avoid the > flush in case it is only the PROCID field that is changing. > > Signed-off-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > target/arm/helper.c | 34 ++++++++++++++++++++++++---------- > 1 file changed, 24 insertions(+), 10 deletions(-) > > diff --git a/target/arm/helper.c b/target/arm/helper.c > index 0f21a077de..1ed7c06313 100644 > --- a/target/arm/helper.c > +++ b/target/arm/helper.c > @@ -551,17 +551,31 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) > static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, > uint64_t value) > { > - ARMCPU *cpu = env_archcpu(env); > - > - if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) > - && !extended_addresses_enabled(env)) { > - /* For VMSA (when not using the LPAE long descriptor page table > - * format) this register includes the ASID, so do a TLB flush. > - * For PMSA it is purely a process ID and no action is needed. > - */ > - tlb_flush(CPU(cpu)); > - } > raw_write(env, ri, value); > + > + /* > + * For VMSA (when not using the LPAE long descriptor page table format) > + * this register includes the ASID. For PMSA it is purely a process ID > + * and no action is needed. > + */ > + if (!arm_feature(env, ARM_FEATURE_PMSA) && > + !extended_addresses_enabled(env)) { > + CPUState *cs = env_cpu(env); > + int asid = extract32(value, 0, 8); > + int idxmask; > + > + switch (ri->secure) { > + case ARM_CP_SECSTATE_S: > + idxmask = ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; > + break; > + case ARM_CP_SECSTATE_NS: > + idxmask = ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; > + break; > + default: > + g_assert_not_reached(); > + } > + tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0); > + } > } > > /* IS variants of TLB operations must affect all cores */ -- Alex Bennée
diff --git a/target/arm/helper.c b/target/arm/helper.c index 0f21a077de..1ed7c06313 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -551,17 +551,31 @@ static void fcse_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) static void contextidr_write(CPUARMState *env, const ARMCPRegInfo *ri, uint64_t value) { - ARMCPU *cpu = env_archcpu(env); - - if (raw_read(env, ri) != value && !arm_feature(env, ARM_FEATURE_PMSA) - && !extended_addresses_enabled(env)) { - /* For VMSA (when not using the LPAE long descriptor page table - * format) this register includes the ASID, so do a TLB flush. - * For PMSA it is purely a process ID and no action is needed. - */ - tlb_flush(CPU(cpu)); - } raw_write(env, ri, value); + + /* + * For VMSA (when not using the LPAE long descriptor page table format) + * this register includes the ASID. For PMSA it is purely a process ID + * and no action is needed. + */ + if (!arm_feature(env, ARM_FEATURE_PMSA) && + !extended_addresses_enabled(env)) { + CPUState *cs = env_cpu(env); + int asid = extract32(value, 0, 8); + int idxmask; + + switch (ri->secure) { + case ARM_CP_SECSTATE_S: + idxmask = ARMMMUIdxBit_S1SE1 | ARMMMUIdxBit_S1SE0; + break; + case ARM_CP_SECSTATE_NS: + idxmask = ARMMMUIdxBit_S12NSE1 | ARMMMUIdxBit_S12NSE0; + break; + default: + g_assert_not_reached(); + } + tlb_set_asid_for_mmuidx(cs, asid, idxmask, 0); + } } /* IS variants of TLB operations must affect all cores */
This is less complex than the LPAE case, but still we now avoid the flush in case it is only the PROCID field that is changing. Signed-off-by: Richard Henderson <richard.henderson@linaro.org> --- target/arm/helper.c | 34 ++++++++++++++++++++++++---------- 1 file changed, 24 insertions(+), 10 deletions(-)