diff mbox series

[OpenWrt-Devel] ar71xx: enable QCA955x SGMII fixup on Mikrotik wAP AC

Message ID 20190714024328.17271-1-champetier.etienne@gmail.com
State Accepted, archived
Delegated to: David Bauer
Headers show
Series [OpenWrt-Devel] ar71xx: enable QCA955x SGMII fixup on Mikrotik wAP AC | expand

Commit Message

Etienne Champetier July 14, 2019, 2:43 a.m. UTC 
fixes intermittent loss of connectivity on 1Gbit port, with log message:
> 803x_aneg_done: SGMII link is not ok

Thanks to David Bauer for pointing me in the right direction
I just had to figure out the right bus_id, which you find in this log:
> ag71xx ag71xx.1: connected to PHY at gpio-1:00 [uid=004dd074, driver=Atheros 8031 ethernet]

Fixes FS#2236

Signed-off-by: Etienne Champetier <champetier.etienne@gmail.com>
---
 .../ar71xx/files/arch/mips/ath79/mach-rbspi.c    | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

Comments

David Bauer July 14, 2019, 11:25 a.m. UTC | #1 
Hi Etienne,

one small remark:

On 14.07.19 04:43, Etienne Champetier wrote:
>  	ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
>  	ath79_eth1_data.mii_bus_dev = &rbwapgsc_phy_device.dev;
>  	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
>  	ath79_eth1_data.phy_mask = BIT(RBWAPGSC_MDIO_PHYADDR);
> +	ath79_eth1_data.enable_sgmii_fixup = 1;

This should be dropped as it's not necessary anymore.

Best wishes
David

>  	ath79_eth1_pll_data.pll_1000 = 0x03000101;
>  	ath79_eth1_pll_data.pll_100 = 0x80000101;
>  	ath79_eth1_pll_data.pll_10 = 0x80001313;
>
Etienne Champetier July 15, 2019, 2:30 a.m. UTC | #2 
Hi David,

Le dim. 14 juil. 2019 à 04:25, David Bauer <mail@david-bauer.net> a écrit :
>
> Hi Etienne,
>
> one small remark:
>
> On 14.07.19 04:43, Etienne Champetier wrote:
> >       ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
> >       ath79_eth1_data.mii_bus_dev = &rbwapgsc_phy_device.dev;
> >       ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
> >       ath79_eth1_data.phy_mask = BIT(RBWAPGSC_MDIO_PHYADDR);
> > +     ath79_eth1_data.enable_sgmii_fixup = 1;
>
> This should be dropped as it's not necessary anymore.

Did some more tests and it's definitely needed (here this is ar71xx &
Linux 4.14)
It's still used for other boards, could you detail why it's not needed
anymore, since what version, reference some commits ?

Thanks
Etienne

>
> Best wishes
> David
>
> >       ath79_eth1_pll_data.pll_1000 = 0x03000101;
> >       ath79_eth1_pll_data.pll_100 = 0x80000101;
> >       ath79_eth1_pll_data.pll_10 = 0x80001313;
> >
David Bauer July 15, 2019, 8:58 a.m. UTC | #3 
Hello Etienne,

On 15.07.19 04:30, Etienne Champetier wrote:
> Hi David,
> 
> Le dim. 14 juil. 2019 à 04:25, David Bauer <mail@david-bauer.net> a écrit :
>>
>> Hi Etienne,
>>
>> one small remark:
>>
>> On 14.07.19 04:43, Etienne Champetier wrote:
>>>       ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
>>>       ath79_eth1_data.mii_bus_dev = &rbwapgsc_phy_device.dev;
>>>       ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
>>>       ath79_eth1_data.phy_mask = BIT(RBWAPGSC_MDIO_PHYADDR);
>>> +     ath79_eth1_data.enable_sgmii_fixup = 1;
>>
>> This should be dropped as it's not necessary anymore.
> 
> Did some more tests and it's definitely needed (here this is ar71xx &
> Linux 4.14)
> It's still used for other boards, could you detail why it's not needed
> anymore, since what version, reference some commits ?

You are right, it is needed. I was only focused on the workaround for the PHY side,
but we indeed explicitly need to enable the MAC side workaround too.

So this looks good to me.

Best wishes
David

> 
> Thanks
> Etienne
> 
>>
>> Best wishes
>> David
>>
>>>       ath79_eth1_pll_data.pll_1000 = 0x03000101;
>>>       ath79_eth1_pll_data.pll_100 = 0x80000101;
>>>       ath79_eth1_pll_data.pll_10 = 0x80001313;
>>>
Etienne Champetier July 17, 2019, 4:17 a.m. UTC | #4 
Hi David,

Le lun. 15 juil. 2019 à 01:58, David Bauer <mail@david-bauer.net> a écrit :
>
> Hello Etienne,
>
> On 15.07.19 04:30, Etienne Champetier wrote:
> > Hi David,
> >
> > Le dim. 14 juil. 2019 à 04:25, David Bauer <mail@david-bauer.net> a écrit :
> >>
> >> Hi Etienne,
> >>
> >> one small remark:
> >>
> >> On 14.07.19 04:43, Etienne Champetier wrote:
> >>>       ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
> >>>       ath79_eth1_data.mii_bus_dev = &rbwapgsc_phy_device.dev;
> >>>       ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
> >>>       ath79_eth1_data.phy_mask = BIT(RBWAPGSC_MDIO_PHYADDR);
> >>> +     ath79_eth1_data.enable_sgmii_fixup = 1;
> >>
> >> This should be dropped as it's not necessary anymore.
> >
> > Did some more tests and it's definitely needed (here this is ar71xx &
> > Linux 4.14)
> > It's still used for other boards, could you detail why it's not needed
> > anymore, since what version, reference some commits ?
>
> You are right, it is needed. I was only focused on the workaround for the PHY side,
> but we indeed explicitly need to enable the MAC side workaround too.
>
> So this looks good to me.

Saw that you applied it to master, I just tested the patch on 19.07, works fine
Do you want me to send the patch again, or can you just cherry-pick it ?
(git cherry-pick 2a7519e29d6cbbe1eb73623ef35add0ef596fb5f)

Thanks
Etienne

>
> Best wishes
> David
>
> >
> > Thanks
> > Etienne
> >
> >>
> >> Best wishes
> >> David
> >>
> >>>       ath79_eth1_pll_data.pll_1000 = 0x03000101;
> >>>       ath79_eth1_pll_data.pll_100 = 0x80000101;
> >>>       ath79_eth1_pll_data.pll_10 = 0x80001313;
> >>>
Petr Štetiar July 17, 2019, 8:32 a.m. UTC | #5 
Etienne Champetier <champetier.etienne@gmail.com> [2019-07-16 21:17:43]:

Hi,

> Saw that you applied it to master, I just tested the patch on 19.07, works fine
> Do you want me to send the patch again, or can you just cherry-pick it ?
> (git cherry-pick 2a7519e29d6cbbe1eb73623ef35add0ef596fb5f)

 git cherry-pick -x 2a7519e29d6cbbe1eb73623ef35add0ef596fb5f

as this is preferred.

-- ynezz
diff mbox series

Patch

diff --git a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
index 96511a4080..1212a91d7e 100644
--- a/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
+++ b/target/linux/ar71xx/files/arch/mips/ath79/mach-rbspi.c
@@ -512,6 +512,18 @@  static struct platform_device rbwapgsc_phy_device = {
 	},
 };
 
+static struct at803x_platform_data rbwapgsc_at803x_data = {
+    .override_sgmii_aneg = 1,
+};
+
+static struct mdio_board_info rbwapgsc_mdio_info[] = {
+    {
+        .bus_id = "gpio-1",
+        .mdio_addr = RBWAPGSC_MDIO_PHYADDR,
+        .platform_data = &rbwapgsc_at803x_data,
+    },
+};
+
 /* RB911L GPIOs */
 #define RB911L_GPIO_BTN_RESET	15
 #define RB911L_GPIO_LED_1	13
@@ -1106,10 +1118,14 @@  static void __init rbwapgsc_setup(void)
 
 	platform_device_register(&rbwapgsc_phy_device);
 
+	mdiobus_register_board_info(rbwapgsc_mdio_info,
+				    ARRAY_SIZE(rbwapgsc_mdio_info));
+
 	ath79_init_mac(ath79_eth1_data.mac_addr, ath79_mac_base, 0);
 	ath79_eth1_data.mii_bus_dev = &rbwapgsc_phy_device.dev;
 	ath79_eth1_data.phy_if_mode = PHY_INTERFACE_MODE_SGMII;
 	ath79_eth1_data.phy_mask = BIT(RBWAPGSC_MDIO_PHYADDR);
+	ath79_eth1_data.enable_sgmii_fixup = 1;
 	ath79_eth1_pll_data.pll_1000 = 0x03000101;
 	ath79_eth1_pll_data.pll_100 = 0x80000101;
 	ath79_eth1_pll_data.pll_10 = 0x80001313;