| Message ID | 20190613143741.15128-1-peter.maydell@linaro.org |
|---|---|
| State | New |
| Headers | show |
| Series | [RISU] arm.risu: Avoid VTRN with Vd == Vm | expand |
On 6/13/19 7:37 AM, Peter Maydell wrote: > The AArch32 VTRN instruction is specified to give an UNKNOWN > result if Vd and Vm are the same register; avoid generating > this in risu output, as we already do for VUZP and VZIP. > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > --- > Alex: this pattern error is why we don't pass your > testcases/aarch32-all/insn_VTRN__INC.risu.bin when compared > with a real Cortex-A7. You probably want to update that. > > arm.risu | 3 ++- > 1 file changed, 2 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson <richard.henderson@linaro.org> r~
On Thu, 13 Jun 2019 at 22:17, Richard Henderson <richard.henderson@linaro.org> wrote: > > On 6/13/19 7:37 AM, Peter Maydell wrote: > > The AArch32 VTRN instruction is specified to give an UNKNOWN > > result if Vd and Vm are the same register; avoid generating > > this in risu output, as we already do for VUZP and VZIP. > > > > Signed-off-by: Peter Maydell <peter.maydell@linaro.org> > > --- > > Alex: this pattern error is why we don't pass your > > testcases/aarch32-all/insn_VTRN__INC.risu.bin when compared > > with a real Cortex-A7. You probably want to update that. > > > > arm.risu | 3 ++- > > 1 file changed, 2 insertions(+), 1 deletion(-) > > Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Applied to risu master, thanks. -- PMM
diff --git a/arm.risu b/arm.risu index 9009e6b..c16d245 100644 --- a/arm.risu +++ b/arm.risu @@ -613,7 +613,8 @@ VCLT0 A1 1111 0011 1 d 11 sz:2 01 vd:4 0 f 100 q m 0 vm:4 VABS A1 1111 0011 1 d 11 sz:2 01 vd:4 0 f 110 q m 0 vm:4 VNEG A1 1111 0011 1 d 11 sz:2 01 vd:4 0 f 111 q m 0 vm:4 VSWP A1 1111 0011 1 d 11 sz:2 10 vd:4 00000 q m 0 vm:4 -VTRN A1 1111 0011 1 d 11 sz:2 10 vd:4 00001 q m 0 vm:4 +# d == m gives UNKNOWN results, so avoid it +VTRN A1 1111 0011 1 d 11 sz:2 10 vd:4 00001 q m 0 vm:4 { ($d != $m) || ($vd != $vm); } # d == m gives UNKNOWN results, so avoid it VUZP A1 1111 0011 1 d 11 sz:2 10 vd:4 00010 q m 0 vm:4 { ($d != $m) || ($vd != $vm); } VZIP A1 1111 0011 1 d 11 sz:2 10 vd:4 00011 q m 0 vm:4 { ($d != $m) || ($vd != $vm); }
The AArch32 VTRN instruction is specified to give an UNKNOWN result if Vd and Vm are the same register; avoid generating this in risu output, as we already do for VUZP and VZIP. Signed-off-by: Peter Maydell <peter.maydell@linaro.org> --- Alex: this pattern error is why we don't pass your testcases/aarch32-all/insn_VTRN__INC.risu.bin when compared with a real Cortex-A7. You probably want to update that. arm.risu | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)