[PULL,30/48] target/arm: Convert VADD to decodetree

Message ID	20190613121433.5246-31-peter.maydell@linaro.org
State	New
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: Peter Maydell <peter.maydell@linaro.org> To: qemu-devel@nongnu.org Date: Thu, 13 Jun 2019 13:14:15 +0100 Message-Id: <20190613121433.5246-31-peter.maydell@linaro.org> In-Reply-To: <20190613121433.5246-1-peter.maydell@linaro.org> References: <20190613121433.5246-1-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Subject: [Qemu-devel] [PULL 30/48] target/arm: Convert VADD to decodetree Precedence: list Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	[PULL,01/48] target/arm: Vectorize USHL and SSHL \| expand [PULL,01/48] target/arm: Vectorize USHL and SSHL [PULL,02/48] target/arm: Use tcg_gen_gvec_bitsel [PULL,03/48] target/arm: Implement NSACR gating of floating point [PULL,04/48] hw/arm/smmuv3: Fix decoding of ID register range [PULL,05/48] hw/core/bus.c: Only the main system bus can have no parent [PULL,07/48] decodetree: Fix comparison of Field [PULL,08/48] target/arm: Add stubs for AArch32 VFP decodetree [PULL,09/48] target/arm: Factor out VFP access checking code [PULL,10/48] target/arm: Fix Cortex-R5F MVFR values [PULL,11/48] target/arm: Explicitly enable VFP short-vectors for aarch32 -cpu max [PULL,12/48] target/arm: Convert the VSEL instructions to decodetree [PULL,13/48] target/arm: Convert VMINNM, VMAXNM to decodetree [PULL,14/48] target/arm: Convert VRINTA/VRINTN/VRINTP/VRINTM to decodetree [PULL,15/48] target/arm: Convert VCVTA/VCVTN/VCVTP/VCVTM to decodetree [PULL,16/48] target/arm: Move the VFP trans_* functions to translate-vfp.inc.c [PULL,17/48] target/arm: Add helpers for VFP register loads and stores [PULL,18/48] target/arm: Convert "double-precision" register moves to decodetree [PULL,19/48] target/arm: Convert "single-precision" register moves to decodetree [PULL,20/48] target/arm: Convert VFP two-register transfer insns to decodetree [PULL,21/48] target/arm: Convert VFP VLDR and VSTR to decodetree [PULL,22/48] target/arm: Convert the VFP load/store multiple insns to decodetree [PULL,23/48] target/arm: Remove VLDR/VSTR/VLDM/VSTM use of cpu_F0s and cpu_F0d [PULL,24/48] target/arm: Convert VFP VMLA to decodetree [PULL,25/48] target/arm: Convert VFP VMLS to decodetree [PULL,26/48] target/arm: Convert VFP VNMLS to decodetree [PULL,27/48] target/arm: Convert VFP VNMLA to decodetree [PULL,28/48] target/arm: Convert VMUL to decodetree [PULL,29/48] target/arm: Convert VNMUL to decodetree [PULL,30/48] target/arm: Convert VADD to decodetree [PULL,31/48] target/arm: Convert VSUB to decodetree [PULL,32/48] target/arm: Convert VDIV to decodetree [PULL,33/48] target/arm: Convert VFP fused multiply-add insns to decodetree [PULL,34/48] target/arm: Convert VMOV (imm) to decodetree [PULL,35/48] target/arm: Convert VABS to decodetree [PULL,36/48] target/arm: Convert VNEG to decodetree [PULL,37/48] target/arm: Convert VSQRT to decodetree [PULL,38/48] target/arm: Convert VMOV (register) to decodetree [PULL,39/48] target/arm: Convert VFP comparison insns to decodetree [PULL,40/48] target/arm: Convert the VCVT-from-f16 insns to decodetree [PULL,41/48] target/arm: Convert the VCVT-to-f16 insns to decodetree [PULL,42/48] target/arm: Convert VFP round insns to decodetree [PULL,43/48] target/arm: Convert double-single precision conversion insns to decodetree [PULL,44/48] target/arm: Convert integer-to-float insns to decodetree [PULL,45/48] target/arm: Convert VJCVT to decodetree [PULL,46/48] target/arm: Convert VCVT fp/fixed-point conversion insns to decodetree [PULL,47/48] target/arm: Convert float-to-integer VCVT insns to decodetree [PULL,48/48] target/arm: Fix short-vector increment behaviour

Message ID

20190613121433.5246-31-peter.maydell@linaro.org

State

New

Headers

From: Peter Maydell <peter.maydell@linaro.org>
To: qemu-devel@nongnu.org
Date: Thu, 13 Jun 2019 13:14:15 +0100
Message-Id: <20190613121433.5246-31-peter.maydell@linaro.org>
In-Reply-To: <20190613121433.5246-1-peter.maydell@linaro.org>
References: <20190613121433.5246-1-peter.maydell@linaro.org>
MIME-Version: 1.0
Content-Transfer-Encoding: 8bit
Subject: [Qemu-devel] [PULL 30/48] target/arm: Convert VADD to decodetree
Precedence: list
Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org
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	<qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>

Series

[PULL,01/48] target/arm: Vectorize USHL and SSHL | expand

Commit Message

Peter Maydell June 13, 2019, 12:14 p.m. UTC

Convert the VADD instruction to decodetree.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/arm/translate-vfp.inc.c | 10 ++++++++++
 target/arm/translate.c         |  6 +-----
 target/arm/vfp.decode          |  5 +++++
 3 files changed, 16 insertions(+), 5 deletions(-)

diff --git a/target/arm/translate-vfp.inc.c b/target/arm/translate-vfp.inc.c
index 4c684f033b6..14aeb25f597 100644
--- a/target/arm/translate-vfp.inc.c
+++ b/target/arm/translate-vfp.inc.c
@@ -1451,3 +1451,13 @@  static bool trans_VNMUL_dp(DisasContext *s, arg_VNMUL_sp *a)
 {
     return do_vfp_3op_dp(s, gen_VNMUL_dp, a->vd, a->vn, a->vm, false);
 }
+
+static bool trans_VADD_sp(DisasContext *s, arg_VADD_sp *a)
+{
+    return do_vfp_3op_sp(s, gen_helper_vfp_adds, a->vd, a->vn, a->vm, false);
+}
+
+static bool trans_VADD_dp(DisasContext *s, arg_VADD_sp *a)
+{
+    return do_vfp_3op_dp(s, gen_helper_vfp_addd, a->vd, a->vn, a->vm, false);
+}
diff --git a/target/arm/translate.c b/target/arm/translate.c
index cf03672db8c..2341479a7c2 100644
--- a/target/arm/translate.c
+++ b/target/arm/translate.c
@@ -1386,7 +1386,6 @@  static inline void gen_vfp_##name(int dp)                             \
     tcg_temp_free_ptr(fpst);                                          \
 }
 
-VFP_OP2(add)
 VFP_OP2(sub)
 VFP_OP2(div)
 
@@ -3111,7 +3110,7 @@  static int disas_vfp_insn(DisasContext *s, uint32_t insn)
             rn = VFP_SREG_N(insn);
 
             switch (op) {
-            case 0 ... 5:
+            case 0 ... 6:
                 /* Already handled by decodetree */
                 return 1;
             default:
@@ -3297,9 +3296,6 @@  static int disas_vfp_insn(DisasContext *s, uint32_t insn)
             for (;;) {
                 /* Perform the calculation.  */
                 switch (op) {
-                case 6: /* add: fn + fm */
-                    gen_vfp_add(dp);
-                    break;
                 case 7: /* sub: fn - fm */
                     gen_vfp_sub(dp);
                     break;
diff --git a/target/arm/vfp.decode b/target/arm/vfp.decode
index 3063fcac23f..d911f12dfd0 100644
--- a/target/arm/vfp.decode
+++ b/target/arm/vfp.decode
@@ -127,3 +127,8 @@  VNMUL_sp     ---- 1110 0.10 .... .... 1010 .1.0 .... \
              vm=%vm_sp vn=%vn_sp vd=%vd_sp
 VNMUL_dp     ---- 1110 0.10 .... .... 1011 .1.0 .... \
              vm=%vm_dp vn=%vn_dp vd=%vd_dp
+
+VADD_sp      ---- 1110 0.11 .... .... 1010 .0.0 .... \
+             vm=%vm_sp vn=%vn_sp vd=%vd_sp
+VADD_dp      ---- 1110 0.11 .... .... 1011 .0.0 .... \
+             vm=%vm_dp vn=%vn_dp vd=%vd_dp

[PULL,30/48] target/arm: Convert VADD to decodetree

Commit Message

Patch