| Message ID | 20190411170355.6882-20-mmaddireddy@nvidia.com |
|---|---|
| State | Superseded |
| Delegated to: | Lorenzo Pieralisi |
| Headers | show |
| Series | Enable Tegra PCIe root port features | expand |
On Thu, Apr 11, 2019 at 10:33:44PM +0530, Manikanta Maddireddy wrote: > Tegra signals PCIe services like AER, PME, etc over legacy IRQ line. > By default service drivers register interrupt routine over MSI IRQ line, > use pcie_pme_disable_msi() function to disable MSI for service drivers. > > PME and AER interrupts registered to MSI without this change > cat /proc/interrupts | grep -i pci > 36: 21 0 0 0 0 0 GICv2 104 Level PCIE > 37: 35 0 0 0 0 0 GICv2 105 Level Tegra PCIe MSI > 76: 0 0 0 0 0 0 Tegra PCIe MSI 0 Edge PCIe PME, aerdrv, PCIe BW notif > > PME and AER interrupts registered to legacy IRQ with this change > cat /proc/interrupts | grep -i pci > 36: 33 0 0 0 0 0 GICv2 104 Level PCIE, PCIe PME, aerdrv, PCIe BW notif > 37: 52 0 0 0 0 0 GICv2 105 Level Tegra PCIe MSI > > Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> > --- > drivers/pci/controller/pci-tegra.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c > index dcfe97711cb5..11be88a394e3 100644 > --- a/drivers/pci/controller/pci-tegra.c > +++ b/drivers/pci/controller/pci-tegra.c > @@ -41,6 +41,7 @@ > #include <soc/tegra/pmc.h> > > #include "../pci.h" > +#include "../pcie/portdrv.h" > > #define INT_PCI_MSI_NR (8 * 32) > > @@ -2724,6 +2725,9 @@ static int tegra_pcie_probe(struct platform_device *pdev) > goto put_resources; > } > > + /* PME events are received over legacy INTR, so disable MSI for PME */ > + pcie_pme_disable_msi(); > + I don't know about Bjorn, but to me it seems like this should be an explicit property of the PCI host bridge rather than some global variable. We already have a couple of flags for similar purposes in struct pci_host_bridge. The above seems like it should always work fine and I can't envision a device where we'd ever have a Tegra PCIe root complex and a different host bridge, so this wouldn't make a difference one way or the other, but this global variable seems like a suboptimal solution to me. Bjorn? Thierry
diff --git a/drivers/pci/controller/pci-tegra.c b/drivers/pci/controller/pci-tegra.c index dcfe97711cb5..11be88a394e3 100644 --- a/drivers/pci/controller/pci-tegra.c +++ b/drivers/pci/controller/pci-tegra.c @@ -41,6 +41,7 @@ #include <soc/tegra/pmc.h> #include "../pci.h" +#include "../pcie/portdrv.h" #define INT_PCI_MSI_NR (8 * 32) @@ -2724,6 +2725,9 @@ static int tegra_pcie_probe(struct platform_device *pdev) goto put_resources; } + /* PME events are received over legacy INTR, so disable MSI for PME */ + pcie_pme_disable_msi(); + pm_runtime_enable(pcie->dev); err = pm_runtime_get_sync(pcie->dev); if (err) {
Tegra signals PCIe services like AER, PME, etc over legacy IRQ line. By default service drivers register interrupt routine over MSI IRQ line, use pcie_pme_disable_msi() function to disable MSI for service drivers. PME and AER interrupts registered to MSI without this change cat /proc/interrupts | grep -i pci 36: 21 0 0 0 0 0 GICv2 104 Level PCIE 37: 35 0 0 0 0 0 GICv2 105 Level Tegra PCIe MSI 76: 0 0 0 0 0 0 Tegra PCIe MSI 0 Edge PCIe PME, aerdrv, PCIe BW notif PME and AER interrupts registered to legacy IRQ with this change cat /proc/interrupts | grep -i pci 36: 33 0 0 0 0 0 GICv2 104 Level PCIE, PCIe PME, aerdrv, PCIe BW notif 37: 52 0 0 0 0 0 GICv2 105 Level Tegra PCIe MSI Signed-off-by: Manikanta Maddireddy <mmaddireddy@nvidia.com> --- drivers/pci/controller/pci-tegra.c | 4 ++++ 1 file changed, 4 insertions(+)