powerpc/64s/hash: Fix assert_slb_presence() use of the slbfee. instruction

Message ID 20190215102020.24346-1-npiggin@gmail.com
State Accepted
Commit 7104dccfd052fde51eecc9972dad9c40bd3e0d11
Headers show
Series
  • powerpc/64s/hash: Fix assert_slb_presence() use of the slbfee. instruction
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Commit Message

Nicholas Piggin Feb. 15, 2019, 10:20 a.m.
The slbfee. instruction must have bit 24 of RB clear, failure to do
so can result in false negatives that result in incorrect assertions.

This is not obvious from the ISA v3.0B document, which only says:

    The hardware ignores the contents of RB 36:38 40:63 -- p.1032

This patch fixes the bug and also clears all other bits from PPC bit
36-63, which is good practice when dealing with reserved or ignored
bits.

Fixes: e15a4fea4d ("powerpc/64s/hash: Add some SLB debugging tests")
Reported-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Tested-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 arch/powerpc/mm/slb.c | 5 +++++
 1 file changed, 5 insertions(+)

Comments

Aneesh Kumar K.V Feb. 15, 2019, 10:27 a.m. | #1
Nicholas Piggin <npiggin@gmail.com> writes:

> The slbfee. instruction must have bit 24 of RB clear, failure to do
> so can result in false negatives that result in incorrect assertions.
>
> This is not obvious from the ISA v3.0B document, which only says:
>
>     The hardware ignores the contents of RB 36:38 40:63 -- p.1032
>
> This patch fixes the bug and also clears all other bits from PPC bit
> 36-63, which is good practice when dealing with reserved or ignored
> bits.
>

Reviewed-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>

> Fixes: e15a4fea4d ("powerpc/64s/hash: Add some SLB debugging tests")
> Reported-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
> Tested-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
>  arch/powerpc/mm/slb.c | 5 +++++
>  1 file changed, 5 insertions(+)
>
> diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
> index bc3914d54e26..5986df48359b 100644
> --- a/arch/powerpc/mm/slb.c
> +++ b/arch/powerpc/mm/slb.c
> @@ -69,6 +69,11 @@ static void assert_slb_presence(bool present, unsigned long ea)
>  	if (!cpu_has_feature(CPU_FTR_ARCH_206))
>  		return;
>  
> +	/*
> +	 * slbfee. requires bit 24 (PPC bit 39) be clear in RB. Hardware
> +	 * ignores all other bits from 0-27, so just clear them all.
> +	 */
> +	ea &= ~((1UL << 28) - 1);

I guess these numbers '28' are derived from the size of the smallest
segment we support. If co can we use ESID_MASK?


>  	asm volatile(__PPC_SLBFEE_DOT(%0, %1) : "=r"(tmp) : "r"(ea) : "cr0");
>  
>  	WARN_ON(present == (tmp == 0));
> -- 
> 2.18.0

Patch

diff --git a/arch/powerpc/mm/slb.c b/arch/powerpc/mm/slb.c
index bc3914d54e26..5986df48359b 100644
--- a/arch/powerpc/mm/slb.c
+++ b/arch/powerpc/mm/slb.c
@@ -69,6 +69,11 @@  static void assert_slb_presence(bool present, unsigned long ea)
 	if (!cpu_has_feature(CPU_FTR_ARCH_206))
 		return;
 
+	/*
+	 * slbfee. requires bit 24 (PPC bit 39) be clear in RB. Hardware
+	 * ignores all other bits from 0-27, so just clear them all.
+	 */
+	ea &= ~((1UL << 28) - 1);
 	asm volatile(__PPC_SLBFEE_DOT(%0, %1) : "=r"(tmp) : "r"(ea) : "cr0");
 
 	WARN_ON(present == (tmp == 0));