Message ID | 88e70713-aa5f-c339-0b60-02cb65dc8c9e@gmail.com |
---|---|
State | Superseded |
Headers | show |
Series | [OpenWrt-Devel,RFC,v2] lantiq: net: ethernet driver with fragments | expand |
Hi Petr, Now i can test new lan driver on VGV7510KW22. Its look really good, with path 904&905 i have 2-4 Mbits more bandwidth, but it seams increasing of descriptors not enough to resole ring full events. Test bench: * O2 box (VGV7510KW22) are connected on 1 GBit switch. * Openwrt master (initramfs) with bootargs = "console=ttyLTQ0,115200"; * Boot via TFTP * disabled: dsl_control, odhcpd, dnsmasq See logs. I will test this 2 pathes on BT5 next days Best regards Yaro On 2/8/19 2:10 PM, Petr Cvek wrote: > I think I've managed to fix the backported driver from vanilla kernel. I > forgot to copy phy_start() call from original driver (that's probably > why it didn't work, I'm booting from NFS and from port 0, so it was > enabled already) and I've added the support for the skb fragments. This > seems to greatly increase the TX throughput. > > In the addition it seems the DMA burst patch doesn't increase the > throughput anymore (TX is probably saturated now, and the code is > better), but the driver supports any burst mode now anyway (there was > just a problem with buffer alignment). > > There were ring full events often, so I've increased the number of > descriptors from 0x40 to 0xc0 and changed the timeout. Maybe it should > work better if the queue is stopped around 50% or something like that. > > Attached: > 0904... - new driver > 0905... - descriptor increase > run.sh - testing script, various iperf3 modes > vanilla... - vanilla openwrt test > z4_hyst... - new driver test (measured with previous patches for SMP ICU > and burst) > > Petr > > _______________________________________________ > openwrt-devel mailing list > openwrt-devel@lists.openwrt.org > https://lists.openwrt.org/mailman/listinfo/openwrt-devel
diff -aurN a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h --- a/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h 2019-01-26 09:37:07.000000000 +0100 +++ b/arch/mips/include/asm/mach-lantiq/xway/xway_dma.h 2019-02-08 12:55:32.693458936 +0100 @@ -19,7 +19,7 @@ #define LTQ_DMA_H__ #define LTQ_DESC_SIZE 0x08 /* each descriptor is 64bit */ -#define LTQ_DESC_NUM 0x40 /* 64 descriptors / channel */ +#define LTQ_DESC_NUM 0xc0 /* 192 descriptors / channel */ #define LTQ_DMA_OWN BIT(31) /* owner bit */ #define LTQ_DMA_C BIT(30) /* complete bit */