| Message ID | 20190118210604.8231-1-linus.walleij@linaro.org |
|---|---|
| State | Changes Requested |
| Delegated to: | Miquel Raynal |
| Headers | show |
| Series | [1/2] mtd: rawnand: fsmc: Reset NAND timings on resume() | expand |
On Fri, 18 Jan 2019 22:06:04 +0100 Linus Walleij <linus.walleij@linaro.org> wrote: > When we go through a suspend/resume cycle the NAND > timings may have been lost so reset the chip. Actually, it's not only about resetting the timings (even if the side effect of calling nand_reset() is that the core re-applies the correct timings through ->setup_data_interface()). We need it to start in a known working state. > > This hardware will autonomously enable/disable the > chip selects depending on what memory is accessed and > chip selects are not software controlled, so we > only lass chip select "0" for "all chips". The FSMC driver only supports single CS chips which explain why you only have to call nand_reset(chip, 0). > > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> > --- > drivers/mtd/nand/raw/fsmc_nand.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c > index c9149a37f8f0..4050843dd35e 100644 > --- a/drivers/mtd/nand/raw/fsmc_nand.c > +++ b/drivers/mtd/nand/raw/fsmc_nand.c > @@ -1164,6 +1164,7 @@ static int fsmc_nand_resume(struct device *dev) > clk_prepare_enable(host->clk); > if (host->dev_timings) > fsmc_nand_setup(host, host->dev_timings); > + nand_reset(&host->nand, 0); > } > > return 0;
Hi Linus, Linus Walleij <linus.walleij@linaro.org> wrote on Fri, 18 Jan 2019 22:06:04 +0100: > When we go through a suspend/resume cycle the NAND > timings may have been lost so reset the chip. > > This hardware will autonomously enable/disable the > chip selects depending on what memory is accessed and > chip selects are not software controlled, so we > only lass chip select "0" for "all chips". > > Signed-off-by: Linus Walleij <linus.walleij@linaro.org> Please Cc: me in your v2. Thanks, Miquèl
diff --git a/drivers/mtd/nand/raw/fsmc_nand.c b/drivers/mtd/nand/raw/fsmc_nand.c index c9149a37f8f0..4050843dd35e 100644 --- a/drivers/mtd/nand/raw/fsmc_nand.c +++ b/drivers/mtd/nand/raw/fsmc_nand.c @@ -1164,6 +1164,7 @@ static int fsmc_nand_resume(struct device *dev) clk_prepare_enable(host->clk); if (host->dev_timings) fsmc_nand_setup(host, host->dev_timings); + nand_reset(&host->nand, 0); } return 0;
When we go through a suspend/resume cycle the NAND timings may have been lost so reset the chip. This hardware will autonomously enable/disable the chip selects depending on what memory is accessed and chip selects are not software controlled, so we only lass chip select "0" for "all chips". Signed-off-by: Linus Walleij <linus.walleij@linaro.org> --- drivers/mtd/nand/raw/fsmc_nand.c | 1 + 1 file changed, 1 insertion(+)