Message ID | 1547832123-32366-1-git-send-email-vgupta@synopsys.com |
---|---|
State | New |
Headers | show |
Series | [ARC] atomics: Add operand to DMB instruction | expand |
Hi, > > 2019-01-18 Vineet Gupta <vgupta@synopsys.com> > > * config/arc/atomic.md: Add operand to DMB instruction > This is ok. I'll push it asap, Claudiu
On 1/20/19 8:19 AM, Claudiu Zissulescu wrote: > Hi, >> 2019-01-18 Vineet Gupta <vgupta@synopsys.com> >> >> * config/arc/atomic.md: Add operand to DMB instruction >> > This is ok. I'll push it asap, > Claudiu Thx, I see it merged into mainline. Can you please backport this to gcc-8-branch as well ? Thx, -Vineet
diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 13890776cc08..09051b816cae 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,7 @@ +2019-01-18 Vineet Gupta <vgupta@synopsys.com> + + * config/arc/atomic.md: Add operand to DMB instruction + 2019-01-18 Richard Biener <rguenther@suse.de> PR tree-optimization/88903 diff --git a/gcc/config/arc/atomic.md b/gcc/config/arc/atomic.md index 562c79a6578e..fe767dfedd5c 100644 --- a/gcc/config/arc/atomic.md +++ b/gcc/config/arc/atomic.md @@ -44,7 +44,7 @@ { if (TARGET_HS) { - return "dmb"; + return "dmb\\t3"; } else {
Atomics use DMB instruction to enforce ordering of loads/stores. Currently gcc generates DMB w/o any arg which is a no-op. Fix that by generating DMB 3 which enforces R+W ordering. It is stricter than what acq/rel expect, but there's no other way. gcc/ 2019-01-18 Vineet Gupta <vgupta@synopsys.com> * config/arc/atomic.md: Add operand to DMB instruction Signed-off-by: Vineet Gupta <vgupta@synopsys.com> --- gcc/ChangeLog | 4 ++++ gcc/config/arc/atomic.md | 2 +- 2 files changed, 5 insertions(+), 1 deletion(-)