Message ID | 1547539894-12898-1-git-send-email-yamada.masahiro@socionext.com |
---|---|
State | Accepted |
Delegated to: | Miquel Raynal |
Headers | show |
Series | mtd: rawnand: denali_dt: remove single anonymous clock support | expand |
Hi Masahiro, Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Tue, 15 Jan 2019 17:11:34 +0900: > Commit 6f1fe97bec34 ("mtd: rawnand: denali_dt: add more clocks based > on IP datasheet") introduced a more correct binding that requires > three named clocks. > > Now that all upstream DT files migrated over to it, remove the single > anonymous clock support. I would love to do that but I think this is against the "DT backward compatibility rule". Anyway, IIRC it is accepted that this kind of rule might be broken if decided per the arch-maintainer (in this case, you I suppose). So if this is really what you want, I'll queue it. Thanks, Miquèl
(+CC Dinh Nguyen) On Tue, Jan 15, 2019 at 5:22 PM Miquel Raynal <miquel.raynal@bootlin.com> wrote: > > Hi Masahiro, > > Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Tue, 15 Jan > 2019 17:11:34 +0900: > > > Commit 6f1fe97bec34 ("mtd: rawnand: denali_dt: add more clocks based > > on IP datasheet") introduced a more correct binding that requires > > three named clocks. > > > > Now that all upstream DT files migrated over to it, remove the single > > anonymous clock support. > > I would love to do that but I think this is against the "DT backward > compatibility rule". Yeah, I know this rule, but we break DT binding from time to time. > Anyway, IIRC it is accepted that this kind of > rule might be broken if decided per the arch-maintainer (in this > case, you I suppose). So if this is really what you want, I'll queue > it. My platform is fine, but this driver is used by SOCFPGA boards as well. I CCed the SOCFPGA maintainer, Dinh Nguyen.
Hi Dinh, Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Wed, 16 Jan 2019 10:27:11 +0900: > (+CC Dinh Nguyen) > > On Tue, Jan 15, 2019 at 5:22 PM Miquel Raynal <miquel.raynal@bootlin.com> wrote: > > > > Hi Masahiro, > > > > Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Tue, 15 Jan > > 2019 17:11:34 +0900: > > > > > Commit 6f1fe97bec34 ("mtd: rawnand: denali_dt: add more clocks based > > > on IP datasheet") introduced a more correct binding that requires > > > three named clocks. > > > > > > Now that all upstream DT files migrated over to it, remove the single > > > anonymous clock support. > > > > I would love to do that but I think this is against the "DT backward > > compatibility rule". > > Yeah, I know this rule, but we break DT binding from time to time. > > > > > Anyway, IIRC it is accepted that this kind of > > rule might be broken if decided per the arch-maintainer (in this > > case, you I suppose). So if this is really what you want, I'll queue > > it. > > My platform is fine, but this driver is used by SOCFPGA boards as well. > > I CCed the SOCFPGA maintainer, Dinh Nguyen. > Can you please share your thoughts on this topic please? Thanks, Miquèl
Hi Dinh, Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Wed, 16 Jan 2019 10:27:11 +0900: > (+CC Dinh Nguyen) > > On Tue, Jan 15, 2019 at 5:22 PM Miquel Raynal <miquel.raynal@bootlin.com> wrote: > > > > Hi Masahiro, > > > > Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Tue, 15 Jan > > 2019 17:11:34 +0900: > > > > > Commit 6f1fe97bec34 ("mtd: rawnand: denali_dt: add more clocks based > > > on IP datasheet") introduced a more correct binding that requires > > > three named clocks. > > > > > > Now that all upstream DT files migrated over to it, remove the single > > > anonymous clock support. > > > > I would love to do that but I think this is against the "DT backward > > compatibility rule". > > Yeah, I know this rule, but we break DT binding from time to time. > > > > > Anyway, IIRC it is accepted that this kind of > > rule might be broken if decided per the arch-maintainer (in this > > case, you I suppose). So if this is really what you want, I'll queue > > it. > > My platform is fine, but this driver is used by SOCFPGA boards as well. > > I CCed the SOCFPGA maintainer, Dinh Nguyen. > Gentle ping on this topic. Thanks, Miquèl
Hi Miquel, Let me review this today. Thanks, Dinh On 1/28/19 4:20 AM, Miquel Raynal wrote: > Hi Dinh, > > Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Wed, 16 Jan > 2019 10:27:11 +0900: > >> (+CC Dinh Nguyen) >> >> On Tue, Jan 15, 2019 at 5:22 PM Miquel Raynal <miquel.raynal@bootlin.com> wrote: >>> >>> Hi Masahiro, >>> >>> Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Tue, 15 Jan >>> 2019 17:11:34 +0900: >>> >>>> Commit 6f1fe97bec34 ("mtd: rawnand: denali_dt: add more clocks based >>>> on IP datasheet") introduced a more correct binding that requires >>>> three named clocks. >>>> >>>> Now that all upstream DT files migrated over to it, remove the single >>>> anonymous clock support. >>> >>> I would love to do that but I think this is against the "DT backward >>> compatibility rule". >> >> Yeah, I know this rule, but we break DT binding from time to time. >> >> >> >>> Anyway, IIRC it is accepted that this kind of >>> rule might be broken if decided per the arch-maintainer (in this >>> case, you I suppose). So if this is really what you want, I'll queue >>> it. >> >> My platform is fine, but this driver is used by SOCFPGA boards as well. >> >> I CCed the SOCFPGA maintainer, Dinh Nguyen. >> > > Gentle ping on this topic. > > > Thanks, > Miquèl >
On 1/28/19 4:20 AM, Miquel Raynal wrote: > Hi Dinh, > > Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Wed, 16 Jan > 2019 10:27:11 +0900: > >> (+CC Dinh Nguyen) >> >> On Tue, Jan 15, 2019 at 5:22 PM Miquel Raynal <miquel.raynal@bootlin.com> wrote: >>> >>> Hi Masahiro, >>> >>> Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Tue, 15 Jan >>> 2019 17:11:34 +0900: >>> >>>> Commit 6f1fe97bec34 ("mtd: rawnand: denali_dt: add more clocks based >>>> on IP datasheet") introduced a more correct binding that requires >>>> three named clocks. >>>> >>>> Now that all upstream DT files migrated over to it, remove the single >>>> anonymous clock support. >>> >>> I would love to do that but I think this is against the "DT backward >>> compatibility rule". >> >> Yeah, I know this rule, but we break DT binding from time to time. >> >> >> >>> Anyway, IIRC it is accepted that this kind of >>> rule might be broken if decided per the arch-maintainer (in this >>> case, you I suppose). So if this is really what you want, I'll queue >>> it. >> >> My platform is fine, but this driver is used by SOCFPGA boards as well. >> >> I CCed the SOCFPGA maintainer, Dinh Nguyen. >> > > Gentle ping on this topic. > This patch looks fine to be. Feel free to add: Tested-by: Dinh Nguyen <dinguyen@kernel.org> Dinh
Hi Dinh, On Thu, 31 Jan 2019 11:24:16 -0600 Dinh Nguyen <dinguyen@kernel.org> wrote: > On 1/28/19 4:20 AM, Miquel Raynal wrote: > > Hi Dinh, > > > > Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Wed, 16 Jan > > 2019 10:27:11 +0900: > > > >> (+CC Dinh Nguyen) > >> > >> On Tue, Jan 15, 2019 at 5:22 PM Miquel Raynal <miquel.raynal@bootlin.com> wrote: > >>> > >>> Hi Masahiro, > >>> > >>> Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Tue, 15 Jan > >>> 2019 17:11:34 +0900: > >>> > >>>> Commit 6f1fe97bec34 ("mtd: rawnand: denali_dt: add more clocks based > >>>> on IP datasheet") introduced a more correct binding that requires > >>>> three named clocks. > >>>> > >>>> Now that all upstream DT files migrated over to it, remove the single > >>>> anonymous clock support. > >>> > >>> I would love to do that but I think this is against the "DT backward > >>> compatibility rule". > >> > >> Yeah, I know this rule, but we break DT binding from time to time. > >> > >> > >> > >>> Anyway, IIRC it is accepted that this kind of > >>> rule might be broken if decided per the arch-maintainer (in this > >>> case, you I suppose). So if this is really what you want, I'll queue > >>> it. > >> > >> My platform is fine, but this driver is used by SOCFPGA boards as well. > >> > >> I CCed the SOCFPGA maintainer, Dinh Nguyen. > >> > > > > Gentle ping on this topic. > > > > This patch looks fine to be. Feel free to add: > > Tested-by: Dinh Nguyen <dinguyen@kernel.org> I think Miquel is waiting for an Acked-by to confirm that you're okay breaking backward compat with old DT. Regards, Boris
Hi Dinh, Boris Brezillon <bbrezillon@kernel.org> wrote on Thu, 31 Jan 2019 18:26:44 +0100: > Hi Dinh, > > On Thu, 31 Jan 2019 11:24:16 -0600 > Dinh Nguyen <dinguyen@kernel.org> wrote: > > > On 1/28/19 4:20 AM, Miquel Raynal wrote: > > > Hi Dinh, > > > > > > Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Wed, 16 Jan > > > 2019 10:27:11 +0900: > > > > > >> (+CC Dinh Nguyen) > > >> > > >> On Tue, Jan 15, 2019 at 5:22 PM Miquel Raynal <miquel.raynal@bootlin.com> wrote: > > >>> > > >>> Hi Masahiro, > > >>> > > >>> Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Tue, 15 Jan > > >>> 2019 17:11:34 +0900: > > >>> > > >>>> Commit 6f1fe97bec34 ("mtd: rawnand: denali_dt: add more clocks based > > >>>> on IP datasheet") introduced a more correct binding that requires > > >>>> three named clocks. > > >>>> > > >>>> Now that all upstream DT files migrated over to it, remove the single > > >>>> anonymous clock support. > > >>> > > >>> I would love to do that but I think this is against the "DT backward > > >>> compatibility rule". > > >> > > >> Yeah, I know this rule, but we break DT binding from time to time. > > >> > > >> > > >> > > >>> Anyway, IIRC it is accepted that this kind of > > >>> rule might be broken if decided per the arch-maintainer (in this > > >>> case, you I suppose). So if this is really what you want, I'll queue > > >>> it. > > >> > > >> My platform is fine, but this driver is used by SOCFPGA boards as well. > > >> > > >> I CCed the SOCFPGA maintainer, Dinh Nguyen. > > >> > > > > > > Gentle ping on this topic. > > > > > > > This patch looks fine to be. Feel free to add: > > > > Tested-by: Dinh Nguyen <dinguyen@kernel.org> > > I think Miquel is waiting for an Acked-by to confirm that you're okay > breaking backward compat with old DT. Yes, I am waiting for your Acked-by. Thanks, Miquèl
On 2/5/19 7:18 AM, Miquel Raynal wrote: > Hi Dinh, > > Boris Brezillon <bbrezillon@kernel.org> wrote on Thu, 31 Jan 2019 > 18:26:44 +0100: > >> Hi Dinh, >> >> On Thu, 31 Jan 2019 11:24:16 -0600 >> Dinh Nguyen <dinguyen@kernel.org> wrote: >> >>> On 1/28/19 4:20 AM, Miquel Raynal wrote: >>>> Hi Dinh, >>>> >>>> Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Wed, 16 Jan >>>> 2019 10:27:11 +0900: >>>> >>>>> (+CC Dinh Nguyen) >>>>> >>>>> On Tue, Jan 15, 2019 at 5:22 PM Miquel Raynal <miquel.raynal@bootlin.com> wrote: >>>>>> >>>>>> Hi Masahiro, >>>>>> >>>>>> Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Tue, 15 Jan >>>>>> 2019 17:11:34 +0900: >>>>>> >>>>>>> Commit 6f1fe97bec34 ("mtd: rawnand: denali_dt: add more clocks based >>>>>>> on IP datasheet") introduced a more correct binding that requires >>>>>>> three named clocks. >>>>>>> >>>>>>> Now that all upstream DT files migrated over to it, remove the single >>>>>>> anonymous clock support. >>>>>> >>>>>> I would love to do that but I think this is against the "DT backward >>>>>> compatibility rule". >>>>> >>>>> Yeah, I know this rule, but we break DT binding from time to time. >>>>> >>>>> >>>>> >>>>>> Anyway, IIRC it is accepted that this kind of >>>>>> rule might be broken if decided per the arch-maintainer (in this >>>>>> case, you I suppose). So if this is really what you want, I'll queue >>>>>> it. >>>>> >>>>> My platform is fine, but this driver is used by SOCFPGA boards as well. >>>>> >>>>> I CCed the SOCFPGA maintainer, Dinh Nguyen. >>>>> >>>> >>>> Gentle ping on this topic. >>>> >>> >>> This patch looks fine to be. Feel free to add: >>> >>> Tested-by: Dinh Nguyen <dinguyen@kernel.org> >> >> I think Miquel is waiting for an Acked-by to confirm that you're okay >> breaking backward compat with old DT. > > Yes, I am waiting for your Acked-by. > > Acked-by: Dinh Nguyen <dinguyen@kernel.org> Dinh
Hi Dinh, Dinh Nguyen <dinguyen@kernel.org> wrote on Thu, 7 Feb 2019 12:17:50 -0600: > On 2/5/19 7:18 AM, Miquel Raynal wrote: > > Hi Dinh, > > > > Boris Brezillon <bbrezillon@kernel.org> wrote on Thu, 31 Jan 2019 > > 18:26:44 +0100: > > > >> Hi Dinh, > >> > >> On Thu, 31 Jan 2019 11:24:16 -0600 > >> Dinh Nguyen <dinguyen@kernel.org> wrote: > >> > >>> On 1/28/19 4:20 AM, Miquel Raynal wrote: > >>>> Hi Dinh, > >>>> > >>>> Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Wed, 16 Jan > >>>> 2019 10:27:11 +0900: > >>>> > >>>>> (+CC Dinh Nguyen) > >>>>> > >>>>> On Tue, Jan 15, 2019 at 5:22 PM Miquel Raynal <miquel.raynal@bootlin.com> wrote: > >>>>>> > >>>>>> Hi Masahiro, > >>>>>> > >>>>>> Masahiro Yamada <yamada.masahiro@socionext.com> wrote on Tue, 15 Jan > >>>>>> 2019 17:11:34 +0900: > >>>>>> > >>>>>>> Commit 6f1fe97bec34 ("mtd: rawnand: denali_dt: add more clocks based > >>>>>>> on IP datasheet") introduced a more correct binding that requires > >>>>>>> three named clocks. > >>>>>>> > >>>>>>> Now that all upstream DT files migrated over to it, remove the single > >>>>>>> anonymous clock support. > >>>>>> > >>>>>> I would love to do that but I think this is against the "DT backward > >>>>>> compatibility rule". > >>>>> > >>>>> Yeah, I know this rule, but we break DT binding from time to time. > >>>>> > >>>>> > >>>>> > >>>>>> Anyway, IIRC it is accepted that this kind of > >>>>>> rule might be broken if decided per the arch-maintainer (in this > >>>>>> case, you I suppose). So if this is really what you want, I'll queue > >>>>>> it. > >>>>> > >>>>> My platform is fine, but this driver is used by SOCFPGA boards as well. > >>>>> > >>>>> I CCed the SOCFPGA maintainer, Dinh Nguyen. > >>>>> > >>>> > >>>> Gentle ping on this topic. > >>>> > >>> > >>> This patch looks fine to be. Feel free to add: > >>> > >>> Tested-by: Dinh Nguyen <dinguyen@kernel.org> > >> > >> I think Miquel is waiting for an Acked-by to confirm that you're okay > >> breaking backward compat with old DT. > > > > Yes, I am waiting for your Acked-by. > > > > > > Acked-by: Dinh Nguyen <dinguyen@kernel.org> > > Dinh Applied to nand/next. Thanks, Miquèl
diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index 7c6a8a4..0b5ae24 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -109,25 +109,17 @@ static int denali_dt_probe(struct platform_device *pdev) if (IS_ERR(denali->host)) return PTR_ERR(denali->host); - /* - * A single anonymous clock is supported for the backward compatibility. - * New platforms should support all the named clocks. - */ dt->clk = devm_clk_get(dev, "nand"); if (IS_ERR(dt->clk)) - dt->clk = devm_clk_get(dev, NULL); - if (IS_ERR(dt->clk)) { - dev_err(dev, "no clk available\n"); return PTR_ERR(dt->clk); - } dt->clk_x = devm_clk_get(dev, "nand_x"); if (IS_ERR(dt->clk_x)) - dt->clk_x = NULL; + return PTR_ERR(dt->clk_x); dt->clk_ecc = devm_clk_get(dev, "ecc"); if (IS_ERR(dt->clk_ecc)) - dt->clk_ecc = NULL; + return PTR_ERR(dt->clk_ecc); ret = clk_prepare_enable(dt->clk); if (ret) @@ -141,19 +133,8 @@ static int denali_dt_probe(struct platform_device *pdev) if (ret) goto out_disable_clk_x; - if (dt->clk_x) { - denali->clk_rate = clk_get_rate(dt->clk); - denali->clk_x_rate = clk_get_rate(dt->clk_x); - } else { - /* - * Hardcode the clock rates for the backward compatibility. - * This works for both SOCFPGA and UniPhier. - */ - dev_notice(dev, - "necessary clock is missing. default clock rates are used.\n"); - denali->clk_rate = 50000000; - denali->clk_x_rate = 200000000; - } + denali->clk_rate = clk_get_rate(dt->clk); + denali->clk_x_rate = clk_get_rate(dt->clk_x); ret = denali_init(denali); if (ret)
Commit 6f1fe97bec34 ("mtd: rawnand: denali_dt: add more clocks based on IP datasheet") introduced a more correct binding that requires three named clocks. Now that all upstream DT files migrated over to it, remove the single anonymous clock support. Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com> --- drivers/mtd/nand/raw/denali_dt.c | 27 ++++----------------------- 1 file changed, 4 insertions(+), 23 deletions(-)