diff mbox series

[v2,11/15] hw/npu2-opencapi: FIR masking for mixed setups

Message ID 336d5f4ecbec960b04ac2dff16e4d99b2b25bab7.1547168645.git-series.andrew.donnellan@au1.ibm.com
State Changes Requested
Headers show
Series Support OpenCAPI and NVLink devices on same NPU on Witherspoon | expand

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Commit Message

Andrew Donnellan Jan. 11, 2019, 1:09 a.m. UTC 
When setting up an NPU with an OpenCAPI device, we need to mask the FIR
bits for NDL Stall/NoStall, which are used for a different purpose on
OpenCAPI vs NVLink.

Currently, we just mask the bits for all links/DLs. When we support mixed
setups of OpenCAPI + NVLink on the same NPU, we don't want to mask all the
bits.

Only mask the FIR bits for the specific links which are OpenCAPI.

Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>
---
 hw/npu2-opencapi.c | 30 +++++++++++++++++++++---------
 1 file changed, 21 insertions(+), 9 deletions(-)

Comments

Alexey Kardashevskiy Jan. 21, 2019, 6:53 a.m. UTC | #1 
On 11/01/2019 12:09, Andrew Donnellan wrote:
> When setting up an NPU with an OpenCAPI device, we need to mask the FIR
> bits for NDL Stall/NoStall, which are used for a different purpose on
> OpenCAPI vs NVLink.
> 
> Currently, we just mask the bits for all links/DLs. When we support mixed
> setups of OpenCAPI + NVLink on the same NPU, we don't want to mask all the
> bits.
> 
> Only mask the FIR bits for the specific links which are OpenCAPI.
> 
> Signed-off-by: Andrew Donnellan <andrew.donnellan@au1.ibm.com>
> Reviewed-by: Frederic Barrat <fbarrat@linux.ibm.com>

Reviewed-by: Alexey Kardashevskiy <aik@ozlabs.ru>

> ---
>  hw/npu2-opencapi.c | 30 +++++++++++++++++++++---------
>  1 file changed, 21 insertions(+), 9 deletions(-)
> 
> diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c
> index d3e95a45e9a4..21dfbdd24989 100644
> --- a/hw/npu2-opencapi.c
> +++ b/hw/npu2-opencapi.c
> @@ -1310,7 +1310,8 @@ static void npu2_opencapi_final_fixup(struct phb *phb)
>  
>  static void mask_nvlink_fir(struct npu2 *p)
>  {
> -	uint64_t reg;
> +	uint64_t reg, mask = 0ull;
> +	int link_num;
>  
>  	/*
>  	 * From section 13.1.3.10 of the NPU workbook: "the NV-Link
> @@ -1319,35 +1320,46 @@ static void mask_nvlink_fir(struct npu2 *p)
>  	 * OpenCAPI. Therefore, the corresponding bits in NPU FIR
>  	 * Register 1 must be masked and configured to NOT cause the
>  	 * NPU to go into Freeze or Fence mode or send an Interrupt."
> -	 *
> -	 * FIXME: will need to revisit when mixing nvlink with
> -	 * opencapi. Assumes an opencapi-only setup on both PHYs for
> -	 * now.
>  	 */
>  
> +	for (int i = 0; i < p-> total_devices; i++) {
> +		struct npu2_dev *dev = &p->devices[i];
> +		/* Only mask OpenCAPI links */
> +		if (dev->type != NPU2_DEV_TYPE_OPENCAPI)
> +			continue;
> +
> +		if (dev->brick_index == 2 || dev->brick_index == 3) {
> +			link_num = dev->brick_index - 2;
> +		} else {
> +			link_num = dev->brick_index;
> +		}
> +		mask = SETFIELD(PPC_BITMASK(link_num * 2,
> +					    link_num * 2 + 1),
> +				mask, 0b11);
> +	}
>  	/* Mask FIRs */
>  	xscom_read(p->chip_id, p->xscom_base + NPU2_MISC_FIR_MASK1, &reg);
> -	reg = SETFIELD(PPC_BITMASK(0, 11), reg, 0xFFF);
> +	reg |= mask;
>  	xscom_write(p->chip_id, p->xscom_base + NPU2_MISC_FIR_MASK1, reg);
>  
>  	/* freeze disable */
>  	reg = npu2_scom_read(p->chip_id, p->xscom_base,
>  			NPU2_MISC_FREEZE_ENABLE1, NPU2_MISC_DA_LEN_8B);
> -	reg = SETFIELD(PPC_BITMASK(0, 11), reg, 0);
> +	reg &= ~mask;
>  	npu2_scom_write(p->chip_id, p->xscom_base,
>  			NPU2_MISC_FREEZE_ENABLE1, NPU2_MISC_DA_LEN_8B, reg);
>  
>  	/* fence disable */
>  	reg = npu2_scom_read(p->chip_id, p->xscom_base,
>  			NPU2_MISC_FENCE_ENABLE1, NPU2_MISC_DA_LEN_8B);
> -	reg = SETFIELD(PPC_BITMASK(0, 11), reg, 0);
> +	reg &= ~mask;
>  	npu2_scom_write(p->chip_id, p->xscom_base,
>  			NPU2_MISC_FENCE_ENABLE1, NPU2_MISC_DA_LEN_8B, reg);
>  
>  	/* irq disable */
>  	reg = npu2_scom_read(p->chip_id, p->xscom_base,
>  			NPU2_MISC_IRQ_ENABLE1, NPU2_MISC_DA_LEN_8B);
> -	reg = SETFIELD(PPC_BITMASK(0, 11), reg, 0);
> +	reg &= ~mask;
>  	npu2_scom_write(p->chip_id, p->xscom_base,
>  			NPU2_MISC_IRQ_ENABLE1, NPU2_MISC_DA_LEN_8B, reg);
>  }
>
diff mbox series

Patch

diff --git a/hw/npu2-opencapi.c b/hw/npu2-opencapi.c
index d3e95a45e9a4..21dfbdd24989 100644
--- a/hw/npu2-opencapi.c
+++ b/hw/npu2-opencapi.c
@@ -1310,7 +1310,8 @@  static void npu2_opencapi_final_fixup(struct phb *phb)
 
 static void mask_nvlink_fir(struct npu2 *p)
 {
-	uint64_t reg;
+	uint64_t reg, mask = 0ull;
+	int link_num;
 
 	/*
 	 * From section 13.1.3.10 of the NPU workbook: "the NV-Link
@@ -1319,35 +1320,46 @@  static void mask_nvlink_fir(struct npu2 *p)
 	 * OpenCAPI. Therefore, the corresponding bits in NPU FIR
 	 * Register 1 must be masked and configured to NOT cause the
 	 * NPU to go into Freeze or Fence mode or send an Interrupt."
-	 *
-	 * FIXME: will need to revisit when mixing nvlink with
-	 * opencapi. Assumes an opencapi-only setup on both PHYs for
-	 * now.
 	 */
 
+	for (int i = 0; i < p-> total_devices; i++) {
+		struct npu2_dev *dev = &p->devices[i];
+		/* Only mask OpenCAPI links */
+		if (dev->type != NPU2_DEV_TYPE_OPENCAPI)
+			continue;
+
+		if (dev->brick_index == 2 || dev->brick_index == 3) {
+			link_num = dev->brick_index - 2;
+		} else {
+			link_num = dev->brick_index;
+		}
+		mask = SETFIELD(PPC_BITMASK(link_num * 2,
+					    link_num * 2 + 1),
+				mask, 0b11);
+	}
 	/* Mask FIRs */
 	xscom_read(p->chip_id, p->xscom_base + NPU2_MISC_FIR_MASK1, &reg);
-	reg = SETFIELD(PPC_BITMASK(0, 11), reg, 0xFFF);
+	reg |= mask;
 	xscom_write(p->chip_id, p->xscom_base + NPU2_MISC_FIR_MASK1, reg);
 
 	/* freeze disable */
 	reg = npu2_scom_read(p->chip_id, p->xscom_base,
 			NPU2_MISC_FREEZE_ENABLE1, NPU2_MISC_DA_LEN_8B);
-	reg = SETFIELD(PPC_BITMASK(0, 11), reg, 0);
+	reg &= ~mask;
 	npu2_scom_write(p->chip_id, p->xscom_base,
 			NPU2_MISC_FREEZE_ENABLE1, NPU2_MISC_DA_LEN_8B, reg);
 
 	/* fence disable */
 	reg = npu2_scom_read(p->chip_id, p->xscom_base,
 			NPU2_MISC_FENCE_ENABLE1, NPU2_MISC_DA_LEN_8B);
-	reg = SETFIELD(PPC_BITMASK(0, 11), reg, 0);
+	reg &= ~mask;
 	npu2_scom_write(p->chip_id, p->xscom_base,
 			NPU2_MISC_FENCE_ENABLE1, NPU2_MISC_DA_LEN_8B, reg);
 
 	/* irq disable */
 	reg = npu2_scom_read(p->chip_id, p->xscom_base,
 			NPU2_MISC_IRQ_ENABLE1, NPU2_MISC_DA_LEN_8B);
-	reg = SETFIELD(PPC_BITMASK(0, 11), reg, 0);
+	reg &= ~mask;
 	npu2_scom_write(p->chip_id, p->xscom_base,
 			NPU2_MISC_IRQ_ENABLE1, NPU2_MISC_DA_LEN_8B, reg);
 }