| Message ID | 20191108144716.23829-1-patrick.delaunay@st.com |
|---|---|
| Headers | show |
| Series | usb: host: dwc2: use driver model for PHY and CLOCK | expand |
On 11/8/19 3:47 PM, Patrick Delaunay wrote: > > In this serie I update the DWC2 host driver to use the device tree > information and the associated PHY and CLOCK drivers when they are > available. I'm kinda on the fence whether to add it into current release or not. The patches look generally OK to me. Ley, Simon, can you check this on SoCFPGA ? Bin, can you give it a once-over ? If this looks OK to you, I will add it. [...]
Marek Vasut <marex@denx.de> schrieb am Fr., 8. Nov. 2019, 16:46: > On 11/8/19 3:47 PM, Patrick Delaunay wrote: > > > > In this serie I update the DWC2 host driver to use the device tree > > information and the associated PHY and CLOCK drivers when they are > > available. > > I'm kinda on the fence whether to add it into current release or not. > The patches look generally OK to me. > > Ley, Simon, can you check this on SoCFPGA ? > Gmm, so can try, but I don't have a working setup with USB peripherals attached... I do have USB on the socrates, but currently no cable to connect anything... I could test it to see if I can get the same result saying no attached devices are found, that would mean probing still works correctly... Regards, Simon Bin, can you give it a once-over ? > > If this looks OK to you, I will add it. > > [...] >
Hi Marek, My ci travis build is failing after the last updates (raspberry pi). I am testing a update with sub for clk disable bulk function: https://github.com/patrickdelaunay/u-boot/commit/1d053dd96e6623d02b84654398655a5563ccfdcb Now buikd is ok: https://travis-ci.org/patrickdelaunay/u-boot/builds/609496187 I will push it after the Week end (tuesday). Sorry. Patrick. Le ven. 8 nov. 2019 à 16:55, Simon Goldschmidt < simon.k.r.goldschmidt@gmail.com> a écrit : > Marek Vasut <marex@denx.de> schrieb am Fr., 8. Nov. 2019, 16:46: > > > On 11/8/19 3:47 PM, Patrick Delaunay wrote: > > > > > > In this serie I update the DWC2 host driver to use the device tree > > > information and the associated PHY and CLOCK drivers when they are > > > available. > > > > I'm kinda on the fence whether to add it into current release or not. > > The patches look generally OK to me. > > > > Ley, Simon, can you check this on SoCFPGA ? > > > > Gmm, so can try, but I don't have a working setup with USB peripherals > attached... I do have USB on the socrates, but currently no cable to > connect anything... > > I could test it to see if I can get the same result saying no attached > devices are found, that would mean probing still works correctly... > > Regards, > Simon > > Bin, can you give it a once-over ? > > > > If this looks OK to you, I will add it. > > > > [...] > > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot >
On Sat, Nov 9, 2019 at 4:46 PM Patrick Delaunay <patrick.delaunay73@gmail.com> wrote: > > Hi Marek, > > My ci travis build is failing after the last updates (raspberry pi). I am testing a update with sub for clk disable bulk function: > > https://github.com/patrickdelaunay/u-boot/commit/1d053dd96e6623d02b84654398655a5563ccfdcb > > Now buikd is ok: > https://travis-ci.org/patrickdelaunay/u-boot/builds/609496187 > > I will push it after the Week end (tuesday). With that additional change, it seems to build and work for me (same error message saying USB "Port not available" than without this patch). Regards, Simon > > Sorry. > > Patrick. > > > > Le ven. 8 nov. 2019 à 16:55, Simon Goldschmidt <simon.k.r.goldschmidt@gmail.com> a écrit : >> >> Marek Vasut <marex@denx.de> schrieb am Fr., 8. Nov. 2019, 16:46: >> >> > On 11/8/19 3:47 PM, Patrick Delaunay wrote: >> > > >> > > In this serie I update the DWC2 host driver to use the device tree >> > > information and the associated PHY and CLOCK drivers when they are >> > > available. >> > >> > I'm kinda on the fence whether to add it into current release or not. >> > The patches look generally OK to me. >> > >> > Ley, Simon, can you check this on SoCFPGA ? >> > >> >> Gmm, so can try, but I don't have a working setup with USB peripherals >> attached... I do have USB on the socrates, but currently no cable to >> connect anything... >> >> I could test it to see if I can get the same result saying no attached >> devices are found, that would mean probing still works correctly... >> >> Regards, >> Simon >> >> Bin, can you give it a once-over ? >> > >> > If this looks OK to you, I will add it. >> > >> > [...] >> > >> _______________________________________________ >> U-Boot mailing list >> U-Boot@lists.denx.de >> https://lists.denx.de/listinfo/u-boot
> -----Original Message----- > From: Marek Vasut <marex@denx.de> > Sent: Friday, November 8, 2019 11:43 PM > To: Patrick Delaunay <patrick.delaunay@st.com>; u-boot@lists.denx.de > Cc: simon.k.r.goldschmidt@gmail.com; b.galvani@gmail.com; Michal > Suchanek <msuchanek@suse.de>; Sven Schwermer > <sven@svenschwermer.de>; U-Boot STM32 <uboot-stm32@st-md- > mailman.stormreply.com>; Bin Meng <bmeng.cn@gmail.com>; Tan, Ley > Foon <ley.foon.tan@intel.com> > Subject: Re: [PATCH v2 0/4] usb: host: dwc2: use driver model for PHY and > CLOCK > > On 11/8/19 3:47 PM, Patrick Delaunay wrote: > > > > In this serie I update the DWC2 host driver to use the device tree > > information and the associated PHY and CLOCK drivers when they are > > available. > > I'm kinda on the fence whether to add it into current release or not. > The patches look generally OK to me. > > Ley, Simon, can you check this on SoCFPGA ? There is compilation error for Stratix10. Stratix10 doesn't support clock DM framework yet. So, this patch needs check for CONFIG_CLK when call to all clock DM functions. drivers/usb/host/built-in.o: In function `dwc2_usb_remove': drivers/usb/host/dwc2.c:1441: undefined reference to `clk_disable_bulk' Tested on Agilex, USB is working fine with this patch. Regards Ley Foon > Bin, can you give it a once-over ? > > If this looks OK to you, I will add it. > > [...]
In this serie I update the DWC2 host driver to use the device tree information and the associated PHY and CLOCK drivers when they are available. I test this serie on stm32mp157c-ev1 board, with PHY and CLK support The U-CLASS are provided by: - PHY by USBPHYC driver = ./drivers/phy/phy-stm32-usbphyc.c - CLOCK by RCC clock driver = drivers/clk/clk_stm32mp1.c - RESET by RCC reset driver = drivers/reset/stm32-reset.c And I activate the configuration +CONFIG_USB_DWC2=y PS: it is not the default configuration to avoid conflict with gadget driver To solve a binding issue, I also deactivate the gadget support: by default only one driver is bound to theusbotg_hs node with "snps,dwc2" compatible, and today it is the device one (the first in the driver list). I also need to deactivate hnp-srp support with: &usbotg_hs { /* need to disable ONLY for HOST support */ hnp-srp-disable; }; WARNING: OTG with device or host support is not correctly handle by DWC2 driver (see example for dynamic OTG role in DWC3 driver). The tests executed on the stm32mp157c-ev1 target: STM32MP> usb start starting USB... Bus usb-otg@49000000: USB DWC2 Bus usbh-ehci@5800d000: USB EHCI 1.00 scanning bus usb-otg@49000000 for devices... 2 USB Device(s) found scanning bus usbh-ehci@5800d000 for devices... 3 USB Device(s) found scanning usb for storage devices... 2 Storage Device(s) found STM32MP> usb tree USB device tree: 1 Hub (480 Mb/s, 0mA) | U-Boot Root Hub | +-2 Mass Storage (480 Mb/s, 300mA) Verbatim STORE N GO 070731C8ACD7EE97 1 Hub (480 Mb/s, 0mA) | u-boot EHCI Host Controller | +-2 Hub (480 Mb/s, 2mA) | +-3 Mass Storage (480 Mb/s, 500mA) Generic USB Storage STM32MP> ls usb 0 <DIR> 4096 . <DIR> 4096 .. <DIR> 16384 lost+found <DIR> 4096 record 1490212 xipImage 21058006 vmlinux STM32MP> load usb 0 0xC0000000 vmlinux 21058006 bytes read in 10851 ms (1.9 MiB/s) Changes in v2: - update dev_err - update commit message - change dev_err to dev_dbg for PHY function call - treat dwc2_shutdown_phy error - add clk_disable_bulk in dwc2_usb_remove Patrick Delaunay (4): usb: host: dwc2: add phy support usb: host: dwc2: add clk support usb: host: dwc2: force reset assert usb: host: dwc2: add trace to have clean usb start drivers/usb/host/dwc2.c | 100 +++++++++++++++++++++++++++++++++++++++- 1 file changed, 99 insertions(+), 1 deletion(-)