@@ -53,7 +53,7 @@ (define_insn_reservation "ppc403-three" 1
"iu_40x,iu_40x,iu_40x")
(define_insn_reservation "ppc403-compare" 3
- (and (ior (eq_attr "type" "cmp,compare")
+ (and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc403,ppc405"))
@@ -95,7 +95,7 @@ (define_insn_reservation "ppc440-branch" 1
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-compare" 2
- (and (ior (eq_attr "type" "cmp,compare,cr_logical,delayed_cr,mfcr")
+ (and (ior (eq_attr "type" "cmp,cr_logical,delayed_cr,mfcr")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc440"))
@@ -77,7 +77,7 @@ (define_insn_reservation "ppc476-complex-integer" 1
ppc476_i_pipe")
(define_insn_reservation "ppc476-compare" 4
- (and (ior (eq_attr "type" "compare,mfcr,mfcrf,mtcr,mfjmpr,mtjmpr")
+ (and (ior (eq_attr "type" "mfcr,mfcrf,mtcr,mfjmpr,mtjmpr")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc476"))
@@ -74,7 +74,7 @@ (define_insn_reservation "ppc601-idiv" 36
; compare executes on integer unit, but feeds insns which
; execute on the branch unit.
(define_insn_reservation "ppc601-compare" 3
- (and (ior (eq_attr "type" "cmp,compare")
+ (and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc601"))
@@ -93,7 +93,7 @@ (define_insn_reservation "ppc603-idiv" 37
"iu_603*37")
(define_insn_reservation "ppc603-compare" 3
- (and (ior (eq_attr "type" "cmp,compare")
+ (and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc603"))
@@ -147,7 +147,7 @@ (define_insn_reservation "ppc620-ldiv" 37
"mciu_6xx*36")
(define_insn_reservation "ppc604-compare" 3
- (and (ior (eq_attr "type" "cmp,compare")
+ (and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
@@ -108,7 +108,7 @@ (define_insn_reservation "ppc7450-idiv" 23
"ppc7450_du,mciu_7450*23")
(define_insn_reservation "ppc7450-compare" 2
- (and (ior (eq_attr "type" "cmp,compare")
+ (and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc7450"))
@@ -101,7 +101,7 @@ (define_insn_reservation "ppc750-idiv" 19
"ppc750_du,iu1_7xx*19")
(define_insn_reservation "ppc750-compare" 2
- (and (ior (eq_attr "type" "cmp,compare")
+ (and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc750,ppc7400"))
@@ -84,7 +84,7 @@ (define_reservation "ppc8540_su_stage0"
;; Simple SU insns
(define_insn_reservation "ppc8540_su" 1
- (and (eq_attr "type" "integer,add,logical,insert,cmp,compare,\
+ (and (eq_attr "type" "integer,add,logical,insert,cmp,\
shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
@@ -201,17 +201,15 @@ (define_insn_reservation "cell-cmp" 1
;; add, addo, sub, subo, alter cr0, rldcli, rlwinm
(define_insn_reservation "cell-fast-cmp" 2
- (and (ior (eq_attr "type" "compare")
- (and (eq_attr "type" "add,logical,shift,exts")
- (eq_attr "dot" "yes")))
+ (and (eq_attr "type" "add,logical,shift,exts")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "not"))
"slot01,fxu_cell")
(define_insn_reservation "cell-cmp-microcoded" 9
- (and (ior (eq_attr "type" "compare")
- (and (eq_attr "type" "add,logical,shift,exts")
- (eq_attr "dot" "yes")))
+ (and (eq_attr "type" "add,logical,shift,exts")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "always"))
"slot0+slot1,fxu_cell,fxu_cell*7")
@@ -83,7 +83,7 @@ (define_reservation "ppce300c3_iu_stage0"
;; Compares can be executed either one of the IU or SRU
(define_insn_reservation "ppce300c3_cmp" 1
- (and (ior (eq_attr "type" "cmp,compare")
+ (and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
@@ -70,7 +70,7 @@ (define_reservation "e500mc_su_stage0"
;; Simple SU insns.
(define_insn_reservation "e500mc_su" 1
- (and (eq_attr "type" "integer,add,logical,insert,cmp,compare,\
+ (and (eq_attr "type" "integer,add,logical,insert,cmp,\
shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
@@ -79,7 +79,7 @@ (define_insn_reservation "e500mc64_su" 1
"e500mc64_decode,e500mc64_issue+e500mc64_su_stage0+e500mc64_retire")
(define_insn_reservation "e500mc64_su2" 2
- (and (ior (eq_attr "type" "cmp,compare,trap")
+ (and (ior (eq_attr "type" "cmp,trap")
(and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
@@ -65,7 +65,7 @@ (define_insn_reservation "e5500_sfx" 1
"e5500_decode,e5500_sfx")
(define_insn_reservation "e5500_sfx2" 2
- (and (ior (eq_attr "type" "cmp,compare,trap")
+ (and (ior (eq_attr "type" "cmp,trap")
(and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
@@ -69,7 +69,7 @@ (define_insn_reservation "e6500_sfx" 1
"e6500_decode,e6500_sfx")
(define_insn_reservation "e6500_sfx2" 2
- (and (ior (eq_attr "type" "cmp,compare,trap")
+ (and (ior (eq_attr "type" "cmp,trap")
(and (eq_attr "type" "add,logical,exts")
(eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
@@ -69,7 +69,7 @@ (define_insn_reservation "mpccore-idiv" 6
"mciu_mpc*6")
(define_insn_reservation "mpccore-compare" 3
- (and (ior (eq_attr "type" "cmp,compare")
+ (and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "mpccore"))
@@ -257,9 +257,8 @@ (define_insn_reservation "power4-cmp" 3
"iq_power4")
(define_insn_reservation "power4-compare" 2
- (and (ior (eq_attr "type" "compare")
- (and (eq_attr "type" "shift,exts")
- (eq_attr "dot" "yes")))
+ (and (eq_attr "type" "shift,exts")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
((iu1_power4,iu2_power4)\
@@ -210,9 +210,8 @@ (define_insn_reservation "power5-cmp" 3
"iq_power5")
(define_insn_reservation "power5-compare" 2
- (and (ior (eq_attr "type" "compare")
- (and (eq_attr "type" "shift,exts")
- (eq_attr "dot" "yes")))
+ (and (eq_attr "type" "shift,exts")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5,iu2_power5")
@@ -334,9 +334,8 @@ (define_insn_reservation "power6-cmp" 1
"FXU_power6")
(define_insn_reservation "power6-compare" 1
- (and (ior (eq_attr "type" "compare")
- (and (eq_attr "type" "exts")
- (eq_attr "dot" "yes")))
+ (and (eq_attr "type" "exts")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "power6"))
"FXU_power6")
@@ -203,9 +203,8 @@ (define_insn_reservation "power7-cmp" 1
"DU_power7,FXU_power7")
(define_insn_reservation "power7-compare" 2
- (and (ior (eq_attr "type" "compare")
- (and (eq_attr "type" "shift,exts")
- (eq_attr "dot" "yes")))
+ (and (eq_attr "type" "shift,exts")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "power7"))
"DU2F_power7,FXU_power7,FXU_power7")
@@ -212,12 +212,10 @@ (define_insn_reservation "power8-fast-compare" 2
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
-; compare : rldicl./exts./etc
-; shift with dot : rlwinm./slwi./rlwnm./slw./etc
+; exts/shift with dot : rldicl./exts./rlwinm./slwi./rlwnm./slw./etc
(define_insn_reservation "power8-compare" 2
- (and (ior (eq_attr "type" "compare")
- (and (eq_attr "type" "shift,exts")
- (eq_attr "dot" "yes")))
+ (and (eq_attr "type" "shift,exts")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,FXU_power8,FXU_power8")
@@ -26696,7 +26696,6 @@ rs6000_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost)
switch (get_attr_type (dep_insn))
{
case TYPE_CMP:
- case TYPE_COMPARE:
case TYPE_FPCOMPARE:
case TYPE_CR_LOGICAL:
case TYPE_DELAYED_CR:
@@ -26753,7 +26752,6 @@ rs6000_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost)
case TYPE_INTEGER:
case TYPE_ADD:
case TYPE_LOGICAL:
- case TYPE_COMPARE:
case TYPE_EXTS:
case TYPE_INSERT:
{
@@ -26817,7 +26815,6 @@ rs6000_adjust_cost (rtx_insn *insn, rtx link, rtx_insn *dep_insn, int cost)
case TYPE_INTEGER:
case TYPE_ADD:
case TYPE_LOGICAL:
- case TYPE_COMPARE:
case TYPE_EXTS:
case TYPE_INSERT:
{
@@ -26993,7 +26990,6 @@ is_cracked_insn (rtx_insn *insn)
|| ((type == TYPE_FPLOAD || type == TYPE_FPSTORE)
&& get_attr_update (insn) == UPDATE_YES)
|| type == TYPE_DELAYED_CR
- || type == TYPE_COMPARE
|| (type == TYPE_EXTS
&& get_attr_dot (insn) == DOT_YES)
|| (type == TYPE_SHIFT
@@ -27875,7 +27871,6 @@ insn_must_be_first_in_group (rtx_insn *insn)
case TYPE_MFCRF:
case TYPE_MTCR:
case TYPE_DIV:
- case TYPE_COMPARE:
case TYPE_ISYNC:
case TYPE_LOAD_L:
case TYPE_STORE_C:
@@ -27916,7 +27911,6 @@ insn_must_be_first_in_group (rtx_insn *insn)
case TYPE_MFCR:
case TYPE_MFCRF:
case TYPE_MTCR:
- case TYPE_COMPARE:
case TYPE_SYNC:
case TYPE_ISYNC:
case TYPE_LOAD_L:
@@ -168,7 +168,6 @@ (define_attr "type"
load,store,fpload,fpstore,vecload,vecstore,
cmp,
branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
- compare,
cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
brinc,
@@ -254,8 +253,7 @@ (define_attr "cpu"
;; If this instruction is microcoded on the CELL processor
; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
(define_attr "cell_micro" "not,conditional,always"
- (if_then_else (ior (eq_attr "type" "compare")
- (and (eq_attr "type" "shift,exts,mul")
+ (if_then_else (ior (and (eq_attr "type" "shift,exts,mul")
(eq_attr "dot" "yes"))
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes"))
@@ -99,7 +99,7 @@ (define_insn_reservation "rs64a-ldiv" 66
"mciu_rs64*66")
(define_insn_reservation "rs64a-compare" 3
- (and (ior (eq_attr "type" "cmp,compare")
+ (and (ior (eq_attr "type" "cmp")
(and (eq_attr "type" "add,logical,shift,exts")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "rs64a"))