diff mbox

[1/6] rs6000: Remove "O" alternative from lshrsi3

Message ID 7e27608c0046f8b5d09895bd504ab07abb80ee15.1403400402.git.segher@kernel.crashing.org
State New
Headers show

Commit Message

Segher Boessenkool June 22, 2014, 2:46 a.m. UTC 
Nothing will ever generate RTL matching this alternative.  Maybe long
ago this was needed, but not anymore.

Bootstrapped and tested on powerpc64-linux, {-m64,-m64/-mtune=power8,
-m32,-m32/-mpowerpc64}, no regressions.  Okay to apply?


Segher


2014-06-21  Segher Boessenkool  <segher@kernel.crashing.org>

gcc/
	* config/rs6000/rs6000.md (lshrsi3, and its two dot patterns):
	Remove "O" alternative.

---
 gcc/config/rs6000/rs6000.md | 43 +++++++++++++++++++------------------------
 1 file changed, 19 insertions(+), 24 deletions(-)

Comments

David Edelsohn June 22, 2014, 2:56 p.m. UTC | #1 
On Sat, Jun 21, 2014 at 10:46 PM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> Nothing will ever generate RTL matching this alternative.  Maybe long
> ago this was needed, but not anymore.

Can you provide some reference for that assertion?

At some point GCC created shifts with zero shift count. It probably
does not, but does a generic optimization prevent this?

Thanks, David
Segher Boessenkool June 22, 2014, 3:40 p.m. UTC | #2 
> > Nothing will ever generate RTL matching this alternative.  Maybe long
> > ago this was needed, but not anymore.
> 
> Can you provide some reference for that assertion?
> 
> At some point GCC created shifts with zero shift count. It probably
> does not, but does a generic optimization prevent this?

All other SI shifts and all DI shifts do not have this.

The "O" alternative is not needed for correctness; "i" is still there.
With the patch, lshrsi3 by 0 generates a "srw" instead of a "mr".
Not a big deal since this can only happen (if at all) with optimisation
turned off.

Shifts by zero are not canonical RTL.  I checked everything in rs6000/
and nothing calls anything with lshr in the name with a shift count
of 0 (which is how almost all non-canonical RTL is created, for rs6000
at least: directly by the backend itself).

The code was added in 1996 ("Try to fix inline of fp/int convert");
sadly, our mail archives do not go that far back.  It's not clear to
me what exactly it fixed (or did not fix).  Looks like one of those
gen_lshrsi3(..., 0) things, if I had to guess.


Segher
David Edelsohn June 22, 2014, 4:33 p.m. UTC | #3 
On Sat, Jun 21, 2014 at 10:46 PM, Segher Boessenkool
<segher@kernel.crashing.org> wrote:
> Nothing will ever generate RTL matching this alternative.  Maybe long
> ago this was needed, but not anymore.
>
> Bootstrapped and tested on powerpc64-linux, {-m64,-m64/-mtune=power8,
> -m32,-m32/-mpowerpc64}, no regressions.  Okay to apply?
>
>
> Segher
>
>
> 2014-06-21  Segher Boessenkool  <segher@kernel.crashing.org>
>
> gcc/
>         * config/rs6000/rs6000.md (lshrsi3, and its two dot patterns):
>         Remove "O" alternative.

Okay.

Thanks, David
diff mbox

Patch

diff --git a/gcc/config/rs6000/rs6000.md b/gcc/config/rs6000/rs6000.md
index c6e85b3..9d92d8f 100644
--- a/gcc/config/rs6000/rs6000.md
+++ b/gcc/config/rs6000/rs6000.md
@@ -4537,16 +4537,15 @@  (define_split
   "")
 
 (define_insn "lshrsi3"
-  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r")
-	(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r")
-		     (match_operand:SI 2 "reg_or_cint_operand" "O,r,i")))]
+  [(set (match_operand:SI 0 "gpc_reg_operand" "=r,r")
+	(lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r")
+		     (match_operand:SI 2 "reg_or_cint_operand" "r,i")))]
   ""
   "@
-  mr %0,%1
   srw %0,%1,%2
   srwi %0,%1,%h2"
-  [(set_attr "type" "integer,shift,shift")
-   (set_attr "var_shift" "no,yes,no")])
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no")])
 
 (define_insn "*lshrsi3_64"
   [(set (match_operand:DI 0 "gpc_reg_operand" "=r,r")
@@ -4561,23 +4560,21 @@  (define_insn "*lshrsi3_64"
    (set_attr "var_shift" "yes,no")])
 
 (define_insn ""
-  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,x,?y,?y,?y")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
+  [(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
+	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
+				 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
 		    (const_int 0)))
-   (clobber (match_scratch:SI 3 "=X,r,r,X,r,r"))]
+   (clobber (match_scratch:SI 3 "=r,r,r,r"))]
   "TARGET_32BIT"
   "@
-   mr. %1,%1
    srw. %3,%1,%2
    srwi. %3,%1,%h2
    #
-   #
    #"
-  [(set_attr "type" "logical,shift,shift,shift,shift,shift")
-   (set_attr "var_shift" "no,yes,no,no,yes,no")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
    (set_attr "dot" "yes")
-   (set_attr "length" "4,4,4,8,8,8")])
+   (set_attr "length" "4,4,8,8")])
 
 (define_split
   [(set (match_operand:CC 0 "cc_reg_not_cr0_operand" "")
@@ -4594,24 +4591,22 @@  (define_split
   "")
 
 (define_insn ""
-  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,x,?y,?y,?y")
-	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r,r,r")
-				 (match_operand:SI 2 "reg_or_cint_operand" "O,r,i,O,r,i"))
+  [(set (match_operand:CC 3 "cc_reg_operand" "=x,x,?y,?y")
+	(compare:CC (lshiftrt:SI (match_operand:SI 1 "gpc_reg_operand" "r,r,r,r")
+				 (match_operand:SI 2 "reg_or_cint_operand" "r,i,r,i"))
 		    (const_int 0)))
-   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r,r,r")
+   (set (match_operand:SI 0 "gpc_reg_operand" "=r,r,r,r")
 	(lshiftrt:SI (match_dup 1) (match_dup 2)))]
   "TARGET_32BIT"
   "@
-   mr. %0,%1
    srw. %0,%1,%2
    srwi. %0,%1,%h2
    #
-   #
    #"
-  [(set_attr "type" "logical,shift,shift,shift,shift,shift")
-   (set_attr "var_shift" "no,yes,no,no,yes,no")
+  [(set_attr "type" "shift")
+   (set_attr "var_shift" "yes,no,yes,no")
    (set_attr "dot" "yes")
-   (set_attr "length" "4,4,4,8,8,8")])
+   (set_attr "length" "4,4,8,8")])
 
 (define_split
   [(set (match_operand:CC 3 "cc_reg_not_cr0_operand" "")