@@ -37,7 +37,7 @@ (define_insn_reservation "ppc403-store" 2
(define_insn_reservation "ppc403-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x")
@@ -54,7 +54,7 @@ (define_insn_reservation "ppc403-three" 1
(define_insn_reservation "ppc403-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc403,ppc405"))
"iu_40x,nothing,bpu_40x")
@@ -53,7 +53,9 @@ (define_insn_reservation "ppc440-fpstore" 3
"ppc440_issue,ppc440_l_pipe")
(define_insn_reservation "ppc440-integer" 1
- (and (eq_attr "type" "integer,insert,shift,trap,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,insert,shift,trap,cntlz,exts,isel")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe|ppc440_j_pipe")
@@ -93,7 +95,9 @@ (define_insn_reservation "ppc440-branch" 1
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-compare" 2
- (and (eq_attr "type" "cmp,fast_compare,compare,cr_logical,delayed_cr,mfcr")
+ (and (ior (eq_attr "type" "cmp,fast_compare,compare,cr_logical,delayed_cr,mfcr")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
@@ -64,7 +64,7 @@ (define_insn_reservation "ppc476-fpstore" 4
(define_insn_reservation "ppc476-simple-integer" 1
(and (ior (eq_attr "type" "integer,insert,exts")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
@@ -79,7 +79,7 @@ (define_insn_reservation "ppc476-complex-integer" 1
(define_insn_reservation "ppc476-compare" 4
(and (ior (eq_attr "type" "compare,fast_compare,mfcr,mfcrf,\
mtcr,mfjmpr,mtjmpr")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
@@ -45,7 +45,7 @@ (define_insn_reservation "ppc601-fpstore" 3
"iu_ppc601+fpu_ppc601")
(define_insn_reservation "ppc601-integer" 1
- (and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
+ (and (ior (eq_attr "type" "integer,add,insert,trap,cntlz,exts,isel")
(and (eq_attr "type" "shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc601"))
@@ -59,7 +59,7 @@ (define_insn_reservation "ppc603-storec" 8
(define_insn_reservation "ppc603-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc603"))
"iu_603")
@@ -94,7 +94,7 @@ (define_insn_reservation "ppc603-idiv" 37
(define_insn_reservation "ppc603-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc603"))
"iu_603,nothing,bpu_603")
@@ -74,7 +74,7 @@ (define_insn_reservation "ppc630-llsc" 4
(define_insn_reservation "ppc604-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"iu1_6xx|iu2_6xx")
@@ -148,7 +148,7 @@ (define_insn_reservation "ppc620-ldiv" 37
(define_insn_reservation "ppc604-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc604,ppc604e,ppc620,ppc630"))
"(iu1_6xx|iu2_6xx)")
@@ -74,7 +74,7 @@ (define_insn_reservation "ppc7450-sync" 35
(define_insn_reservation "ppc7450-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,iu1_7450|iu2_7450|iu3_7450")
@@ -109,7 +109,7 @@ (define_insn_reservation "ppc7450-idiv" 23
(define_insn_reservation "ppc7450-compare" 2
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,(iu1_7450|iu2_7450|iu3_7450)")
@@ -62,7 +62,7 @@ (define_insn_reservation "ppc750-storec" 8
(define_insn_reservation "ppc750-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx|iu2_7xx")
@@ -102,7 +102,7 @@ (define_insn_reservation "ppc750-idiv" 19
(define_insn_reservation "ppc750-compare" 2
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,(iu1_7xx|iu2_7xx)")
@@ -84,7 +84,7 @@ (define_reservation "ppc8540_su_stage0"
;; Simple SU insns
(define_insn_reservation "ppc8540_su" 1
- (and (eq_attr "type" "integer,insert,cmp,compare,fast_compare,\
+ (and (eq_attr "type" "integer,add,insert,cmp,compare,fast_compare,\
shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_su_stage0+ppc8540_retire")
@@ -167,7 +167,7 @@ (define_insn_reservation "cell-vecstore" 1
;; Integer latency is 2 cycles
(define_insn_reservation "cell-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
@@ -202,7 +202,7 @@ (define_insn_reservation "cell-cmp" 1
;; add, addo, sub, subo, alter cr0, rldcli, rlwinm
(define_insn_reservation "cell-fast-cmp" 2
(and (ior (eq_attr "type" "fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "not"))
@@ -210,7 +210,7 @@ (define_insn_reservation "cell-fast-cmp" 2
(define_insn_reservation "cell-cmp-microcoded" 9
(and (ior (eq_attr "type" "fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "cell")
(eq_attr "cell_micro" "always"))
@@ -84,7 +84,7 @@ (define_reservation "ppce300c3_iu_stage0"
;; Compares can be executed either one of the IU or SRU
(define_insn_reservation "ppce300c3_cmp" 1
(and (ior (eq_attr "type" "cmp,compare,fast_compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+(ppce300c3_iu_stage0|ppce300c3_sru_stage0) \
@@ -92,7 +92,9 @@ (define_insn_reservation "ppce300c3_cmp" 1
;; Other one cycle IU insns
(define_insn_reservation "ppce300c3_iu" 1
- (and (eq_attr "type" "integer,insert,isel")
+ (and (ior (eq_attr "type" "integer,insert,isel")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no")))
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0+ppce300c3_retire")
@@ -70,7 +70,7 @@ (define_reservation "e500mc_su_stage0"
;; Simple SU insns.
(define_insn_reservation "e500mc_su" 1
- (and (eq_attr "type" "integer,insert,cmp,compare,fast_compare,\
+ (and (eq_attr "type" "integer,add,insert,cmp,compare,fast_compare,\
shift,trap,cntlz,exts,isel")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_su_stage0+e500mc_retire")
@@ -70,6 +70,8 @@ (define_reservation "e500mc64_su_stage0"
;; Simple SU insns.
(define_insn_reservation "e500mc64_su" 1
(and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "no")
(eq_attr "var_shift" "no")))
@@ -78,6 +80,8 @@ (define_insn_reservation "e500mc64_su" 1
(define_insn_reservation "e500mc64_su2" 2
(and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes"))
(and (eq_attr "type" "shift")
(eq_attr "dot" "yes")
(eq_attr "var_shift" "no")))
@@ -57,13 +57,17 @@ (define_reservation "e5500_sfx"
;; SFX.
(define_insn_reservation "e5500_sfx" 1
(and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
(define_insn_reservation "e5500_sfx2" 2
- (and (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_sfx")
@@ -60,13 +60,17 @@ (define_reservation "e6500_sfx"
;; SFX.
(define_insn_reservation "e6500_sfx" 1
(and (ior (eq_attr "type" "integer,insert,cntlz,exts")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no"))
(and (eq_attr "type" "shift")
(eq_attr "var_shift" "no")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
(define_insn_reservation "e6500_sfx2" 2
- (and (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (ior (eq_attr "type" "cmp,compare,fast_compare,trap")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_sfx")
@@ -42,7 +42,7 @@ (define_insn_reservation "mpccore-fpload" 2
(define_insn_reservation "mpccore-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "mpccore"))
"iu_mpc")
@@ -70,7 +70,7 @@ (define_insn_reservation "mpccore-idiv" 6
(define_insn_reservation "mpccore-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "mpccore"))
"iu_mpc,nothing,bpu_mpc")
@@ -211,7 +211,7 @@ (define_insn_reservation "power4-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power4-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
@@ -250,7 +250,9 @@ (define_insn_reservation "power4-insert" 4
|(iu2_power4,nothing,iu1_power4))")
(define_insn_reservation "power4-cmp" 3
- (and (eq_attr "type" "cmp,fast_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power4"))
"iq_power4")
@@ -167,7 +167,7 @@ (define_insn_reservation "power5-llsc" 11
; Integer latency is 2 cycles
(define_insn_reservation "power5-integer" 2
(and (ior (eq_attr "type" "integer,trap,cntlz,exts,isel,popcnt")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no"))
(and (eq_attr "type" "insert")
(eq_attr "size" "64")))
@@ -203,7 +203,9 @@ (define_insn_reservation "power5-insert" 4
"du1_power5+du2_power5,iu1_power5,nothing,iu2_power5")
(define_insn_reservation "power5-cmp" 3
- (and (eq_attr "type" "cmp,fast_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power5"))
"iq_power5")
@@ -222,7 +222,9 @@ (define_insn_reservation "power6-sync" 11 ; N/A
"LSU_power6")
(define_insn_reservation "power6-integer" 1
- (and (eq_attr "type" "integer")
+ (and (ior (eq_attr "type" "integer")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "power6"))
"FXU_power6")
@@ -336,7 +338,9 @@ (define_insn_reservation "power6-compare" 1
"FXU_power6")
(define_insn_reservation "power6-fast-compare" 1
- (and (eq_attr "type" "fast_compare")
+ (and (ior (eq_attr "type" "fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power6"))
"FXU_power6")
@@ -175,7 +175,7 @@ (define_insn_reservation "power7-sync" 11
; FX Unit
(define_insn_reservation "power7-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,exts,isel,popcnt")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
@@ -196,7 +196,9 @@ (define_insn_reservation "power7-three" 3
"DU_power7+DU_power7+DU_power7,FXU_power7,FXU_power7,FXU_power7")
(define_insn_reservation "power7-cmp" 1
- (and (eq_attr "type" "cmp,fast_compare")
+ (and (ior (eq_attr "type" "cmp,fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
@@ -169,7 +169,7 @@ (define_insn_reservation "power8-sync" 1
; FX Unit
(define_insn_reservation "power8-1cyc" 1
(and (ior (eq_attr "type" "integer,insert,trap,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
@@ -207,7 +207,9 @@ (define_insn_reservation "power8-cmp" 2
; fast_compare : add./and./nor./etc
(define_insn_reservation "power8-fast-compare" 2
- (and (eq_attr "type" "fast_compare")
+ (and (ior (eq_attr "type" "fast_compare")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
@@ -26240,6 +26240,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
break;
}
case TYPE_INTEGER:
+ case TYPE_ADD:
case TYPE_COMPARE:
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
@@ -26303,6 +26304,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
break;
}
case TYPE_INTEGER:
+ case TYPE_ADD:
case TYPE_COMPARE:
case TYPE_FAST_COMPARE:
case TYPE_EXTS:
@@ -159,7 +159,7 @@ (define_c_enum "unspecv"
;; computations.
(define_attr "type"
"integer,two,three,
- shift,insert,
+ add,shift,insert,
mul,halfmul,div,
exts,cntlz,popcnt,isel,
load,store,fpload,fpstore,vecload,vecstore,
@@ -1820,7 +1820,7 @@ (define_insn "*add<mode>3_internal1"
addi %0,%1,%2
addic %0,%1,%2
addis %0,%1,%v2"
- [(set_attr "length" "4,4,4,4")])
+ [(set_attr "type" "add")])
(define_insn "addsi3_high"
[(set (match_operand:SI 0 "gpc_reg_operand" "=b")
@@ -1828,7 +1828,7 @@ (define_insn "addsi3_high"
(high:SI (match_operand 2 "" ""))))]
"TARGET_MACHO && !TARGET_64BIT"
"addis %0,%1,ha16(%2)"
- [(set_attr "length" "4")])
+ [(set_attr "type" "add")])
(define_insn "*add<mode>3_internal2"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,x,?y,?y")
@@ -1842,7 +1842,8 @@ (define_insn "*add<mode>3_internal2"
addic. %3,%1,%2
#
#"
- [(set_attr "type" "fast_compare,compare,compare,compare")
+ [(set_attr "type" "add,compare,compare,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -1874,7 +1875,8 @@ (define_insn "*add<mode>3_internal3"
addic. %0,%1,%2
#
#"
- [(set_attr "type" "fast_compare,compare,compare,compare")
+ [(set_attr "type" "add,compare,compare,compare")
+ (set_attr "dot" "yes")
(set_attr "length" "4,4,8,8")])
(define_split
@@ -2000,7 +2002,8 @@ (define_insn ""
""
"@
subf %0,%2,%1
- subfic %0,%2,%1")
+ subfic %0,%2,%1"
+ [(set_attr "type" "add")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -2012,7 +2015,8 @@ (define_insn ""
"@
subf. %3,%2,%1
#"
- [(set_attr "type" "fast_compare")
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -2042,7 +2046,8 @@ (define_insn ""
"@
subf. %0,%2,%1
#"
- [(set_attr "type" "fast_compare")
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -2087,7 +2092,8 @@ (define_insn "*neg<mode>2_internal"
[(set (match_operand:GPR 0 "gpc_reg_operand" "=r")
(neg:GPR (match_operand:GPR 1 "gpc_reg_operand" "r")))]
""
- "neg %0,%1")
+ "neg %0,%1"
+ [(set_attr "type" "add")])
(define_insn ""
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -2098,7 +2104,8 @@ (define_insn ""
"@
neg. %2,%1
#"
- [(set_attr "type" "fast_compare")
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -2124,7 +2131,8 @@ (define_insn ""
"@
neg. %0,%1
#"
- [(set_attr "type" "fast_compare")
+ [(set_attr "type" "add")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -47,7 +47,7 @@ (define_insn_reservation "rs64a-llsc" 2
(define_insn_reservation "rs64a-integer" 1
(and (ior (eq_attr "type" "integer,insert,trap,cntlz,exts,isel")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "no")))
(eq_attr "cpu" "rs64a"))
"iu_rs64")
@@ -100,7 +100,7 @@ (define_insn_reservation "rs64a-ldiv" 66
(define_insn_reservation "rs64a-compare" 3
(and (ior (eq_attr "type" "cmp,fast_compare,compare")
- (and (eq_attr "type" "shift")
+ (and (eq_attr "type" "add,shift")
(eq_attr "dot" "yes")))
(eq_attr "cpu" "rs64a"))
"iu_rs64,nothing,bpu_rs64")
@@ -34,7 +34,9 @@ (define_cpu_unit "titan_fxu_sh,titan_fxu_wb" "titan_fxu")
;; instructions. It provides its own, dedicated result-bus, so we
;; don't need the titan_fxu_wb reservation to complete.
(define_insn_reservation "titan_fxu_adder" 1
- (and (eq_attr "type" "cmp,fast_compare,trap")
+ (and (ior (eq_attr "type" "cmp,fast_compare,trap")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "yes")))
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh")
@@ -72,7 +74,9 @@ (define_insn_reservation "titan_fxu_div" 34
"titan_issue,titan_fxu_sh")
(define_insn_reservation "titan_fxu_alu" 1
- (and (eq_attr "type" "integer,exts")
+ (and (ior (eq_attr "type" "integer,exts")
+ (and (eq_attr "type" "add")
+ (eq_attr "dot" "no")))
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing,titan_fxu_wb")