@@ -58,22 +58,26 @@ (define_insn_reservation "ppc403-compare" 3
"iu_40x,nothing,bpu_40x")
(define_insn_reservation "ppc403-imul" 4
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc403"))
"iu_40x*4")
(define_insn_reservation "ppc405-imul" 5
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc405"))
"iu_40x*4")
(define_insn_reservation "ppc405-imul2" 3
- (and (eq_attr "type" "imul2")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "16")
(eq_attr "cpu" "ppc405"))
"iu_40x*2")
(define_insn_reservation "ppc405-imul3" 2
- (and (eq_attr "type" "imul3,halfmul")
+ (and (ior (eq_attr "type" "halfmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8")))
(eq_attr "cpu" "ppc405"))
"iu_40x")
@@ -71,12 +71,15 @@ (define_insn_reservation "ppc440-three" 1
ppc440_i_pipe|ppc440_j_pipe,ppc440_i_pipe|ppc440_j_pipe")
(define_insn_reservation "ppc440-imul" 3
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
(define_insn_reservation "ppc440-imul2" 2
- (and (eq_attr "type" "imul2,imul3,halfmul")
+ (and (ior (eq_attr "type" "halfmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")))
(eq_attr "cpu" "ppc440"))
"ppc440_issue,ppc440_i_pipe")
@@ -82,7 +82,7 @@ (define_insn_reservation "ppc476-compare" 4
ppc476_i_pipe")
(define_insn_reservation "ppc476-imul" 4
- (and (eq_attr "type" "imul,imul_compare,imul2,imul3,halfmul")
+ (and (eq_attr "type" "mul,halfmul")
(eq_attr "cpu" "ppc476"))
"ppc476_issue,\
ppc476_i_pipe")
@@ -61,7 +61,7 @@ (define_insn_reservation "ppc601-three" 1
"iu_ppc601,iu_ppc601,iu_ppc601")
(define_insn_reservation "ppc601-imul" 5
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc601"))
"iu_ppc601*5")
@@ -75,12 +75,14 @@ (define_insn_reservation "ppc603-three" 1
; This takes 2 or 3 cycles
(define_insn_reservation "ppc603-imul" 3
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc603"))
"iu_603*2")
(define_insn_reservation "ppc603-imul2" 2
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")
(eq_attr "cpu" "ppc603"))
"iu_603*2")
@@ -89,32 +89,36 @@ (define_insn_reservation "ppc604-three" 1
"iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx,iu1_6xx|iu2_6xx")
(define_insn_reservation "ppc604-imul" 4
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc604"))
"mciu_6xx*2")
(define_insn_reservation "ppc604e-imul" 2
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc604e"))
"mciu_6xx")
(define_insn_reservation "ppc620-imul" 5
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
(define_insn_reservation "ppc620-imul2" 4
- (and (eq_attr "type" "imul2")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "16")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
(define_insn_reservation "ppc620-imul3" 3
- (and (eq_attr "type" "imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*3")
(define_insn_reservation "ppc620-lmul" 7
- (and (eq_attr "type" "lmul,lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "64")
(eq_attr "cpu" "ppc620,ppc630"))
"mciu_6xx*5")
@@ -90,12 +90,14 @@ (define_insn_reservation "ppc7450-three" 1
iu1_7450|iu2_7450|iu3_7450,iu1_7450|iu2_7450|iu3_7450")
(define_insn_reservation "ppc7450-imul" 4
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450*2")
(define_insn_reservation "ppc7450-imul2" 3
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")
(eq_attr "cpu" "ppc7450"))
"ppc7450_du,mciu_7450")
@@ -77,17 +77,20 @@ (define_insn_reservation "ppc750-three" 1
"ppc750_du,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx,iu1_7xx|iu2_7xx")
(define_insn_reservation "ppc750-imul" 4
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx*4")
(define_insn_reservation "ppc750-imul2" 3
- (and (eq_attr "type" "imul2")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "16")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx*2")
(define_insn_reservation "ppc750-imul3" 2
- (and (eq_attr "type" "imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8")
(eq_attr "cpu" "ppc750,ppc7400"))
"ppc750_du,iu1_7xx")
@@ -111,7 +111,7 @@ (define_insn_reservation "ppc8540_branch" 1
;; Multiply
(define_insn_reservation "ppc8540_multiply" 4
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppc8540,ppc8548"))
"ppc8540_decode,ppc8540_issue+ppc8540_mu_stage0,ppc8540_mu_stage1,\
ppc8540_mu_stage2,ppc8540_mu_stage3+ppc8540_retire")
@@ -48,13 +48,15 @@ (define_insn_reservation "ppca2-mtjmpr" 5
;; D.4.8
(define_insn_reservation "ppca2-imul" 1
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16,32")
(eq_attr "cpu" "ppca2"))
"nothing")
;; FIXME: latency and multiplier reservation for 64-bit multiply?
(define_insn_reservation "ppca2-lmul" 6
- (and (eq_attr "type" "lmul,lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "64")
(eq_attr "cpu" "ppca2"))
"mult*3")
@@ -212,25 +212,32 @@ (define_insn_reservation "cell-cmp-microcoded" 9
;; mulld
(define_insn_reservation "cell-lmul" 15
- (and (eq_attr "type" "lmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "64")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*13")
;; mulld. is microcoded
(define_insn_reservation "cell-lmul-cmp" 22
- (and (eq_attr "type" "lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "64")
(eq_attr "cpu" "cell"))
"slot0+slot1,nonpipeline,nonpipeline*20")
;; mulli, 6 cycles
(define_insn_reservation "cell-imul23" 6
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*4")
;; mullw, 9
(define_insn_reservation "cell-imul" 9
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "32")
(eq_attr "cpu" "cell"))
"slot1,nonpipeline,nonpipeline*7")
@@ -102,7 +102,7 @@ (define_insn_reservation "ppce300c3_branch" 1
;; Multiply is non-pipelined but can be executed in any IU
(define_insn_reservation "ppce300c3_multiply" 2
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(ior (eq_attr "cpu" "ppce300c2") (eq_attr "cpu" "ppce300c3")))
"ppce300c3_decode,ppce300c3_issue+ppce300c3_iu_stage0, \
ppce300c3_iu_stage0+ppce300c3_retire")
@@ -91,7 +91,7 @@ (define_insn_reservation "e500mc_three" 1
;; Multiply.
(define_insn_reservation "e500mc_multiply" 4
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppce500mc"))
"e500mc_decode,e500mc_issue+e500mc_mu_stage0,e500mc_mu_stage1,\
e500mc_mu_stage2,e500mc_mu_stage3+e500mc_retire")
@@ -99,7 +99,7 @@ (define_insn_reservation "e500mc64_three" 3
;; Multiply.
(define_insn_reservation "e500mc64_multiply" 4
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "ppce500mc64"))
"e500mc64_decode,e500mc64_issue+e500mc64_mu_stage0,e500mc64_mu_stage1,\
e500mc64_mu_stage2,e500mc64_mu_stage3+e500mc64_retire")
@@ -101,12 +101,16 @@ (define_insn_reservation "e5500_mtjmpr" 1
;; CFX - Multiply.
(define_insn_reservation "e5500_multiply" 4
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0,e5500_cfx_stage1")
(define_insn_reservation "e5500_multiply_i" 5
- (and (eq_attr "type" "imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
+ (ior (eq_attr "dot" "yes")
+ (eq_attr "size" "8,16"))
(eq_attr "cpu" "ppce5500"))
"e5500_decode,e5500_cfx_stage0,\
e5500_cfx_stage0+e5500_cfx_stage1,e5500_cfx_stage1")
@@ -104,12 +104,16 @@ (define_insn_reservation "e6500_mtjmpr" 1
;; CFX - Multiply.
(define_insn_reservation "e6500_multiply" 4
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "32")
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_cfx_stage0,e6500_cfx_stage1")
(define_insn_reservation "e6500_multiply_i" 5
- (and (eq_attr "type" "imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
+ (ior (eq_attr "dot" "yes")
+ (eq_attr "size" "8,16"))
(eq_attr "cpu" "ppce6500"))
"e6500_decode,e6500_cfx_stage0,\
e6500_cfx_stage0+e6500_cfx_stage1,e6500_cfx_stage1")
@@ -57,7 +57,7 @@ (define_insn_reservation "mpccore-three" 1
"iu_mpc,iu_mpc,iu_mpc")
(define_insn_reservation "mpccore-imul" 2
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "mpccore"))
"mciu_mpc")
@@ -261,7 +261,9 @@ (define_insn_reservation "power4-compare" 2
(define_bypass 4 "power4-compare" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
(define_insn_reservation "power4-lmul-cmp" 7
- (and (eq_attr "type" "lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
((iu1_power4*6,iu2_power4)\
@@ -271,7 +273,9 @@ (define_insn_reservation "power4-lmul-cmp" 7
(define_bypass 10 "power4-lmul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
(define_insn_reservation "power4-imul-cmp" 5
- (and (eq_attr "type" "imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power4"))
"(du1_power4+du2_power4|du2_power4+du3_power4|du3_power4+du4_power4),\
((iu1_power4*4,iu2_power4)\
@@ -281,19 +285,24 @@ (define_insn_reservation "power4-imul-cmp" 5
(define_bypass 8 "power4-imul-cmp" "power4-branch,power4-crlogical,power4-delayedcr,power4-mfcr,power4-mfcrf")
(define_insn_reservation "power4-lmul" 7
- (and (eq_attr "type" "lmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power4"))
"(du1_power4|du2_power4|du3_power4|du4_power4),\
(iu1_power4*6|iu2_power4*6)")
(define_insn_reservation "power4-imul" 5
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power4"))
"(du1_power4|du2_power4|du3_power4|du4_power4),\
(iu1_power4*4|iu2_power4*4)")
(define_insn_reservation "power4-imul3" 4
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")
(eq_attr "cpu" "power4"))
"(du1_power4|du2_power4|du3_power4|du4_power4),\
(iu1_power4*3|iu2_power4*3)")
@@ -211,31 +211,40 @@ (define_insn_reservation "power5-compare" 2
(define_bypass 4 "power5-compare" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
(define_insn_reservation "power5-lmul-cmp" 7
- (and (eq_attr "type" "lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5*6,iu2_power5")
(define_bypass 10 "power5-lmul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
(define_insn_reservation "power5-imul-cmp" 5
- (and (eq_attr "type" "imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power5"))
"du1_power5+du2_power5,iu1_power5*4,iu2_power5")
(define_bypass 8 "power5-imul-cmp" "power5-branch,power5-crlogical,power5-delayedcr,power5-mfcr,power5-mfcrf")
(define_insn_reservation "power5-lmul" 7
- (and (eq_attr "type" "lmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power5"))
"(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*6|iu2_power5*6)")
(define_insn_reservation "power5-imul" 5
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power5"))
"(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*4|iu2_power5*4)")
(define_insn_reservation "power5-imul3" 4
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")
(eq_attr "cpu" "power5"))
"(du1_power5|du2_power5|du3_power5|du4_power5),(iu1_power5*3|iu2_power5*3)")
@@ -357,31 +357,40 @@ (define_insn_reservation "power6-var-delayed-compare" 4
"FXU_power6")
(define_insn_reservation "power6-lmul-cmp" 16
- (and (eq_attr "type" "lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-imul-cmp" 16
- (and (eq_attr "type" "imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-lmul" 16
- (and (eq_attr "type" "lmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "64")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-imul" 16
- (and (eq_attr "type" "imul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
+ (eq_attr "size" "32")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
(define_insn_reservation "power6-imul3" 16
- (and (eq_attr "type" "imul2,imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8,16")
(eq_attr "cpu" "power6"))
"(iu1_power6*16+iu2_power6*16+fpu1_power6*16)\
|(iu1_power6*16+iu2_power6*16+fpu2_power6*16)");
@@ -207,12 +207,14 @@ (define_insn_reservation "power7-compare" 2
(define_bypass 3 "power7-cmp,power7-compare" "power7-crlogical,power7-delayedcr")
(define_insn_reservation "power7-mul" 4
- (and (eq_attr "type" "imul,imul2,imul3,lmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
(eq_attr "cpu" "power7"))
"DU_power7,FXU_power7")
(define_insn_reservation "power7-mul-compare" 5
- (and (eq_attr "type" "imul_compare,lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "power7"))
"DU2F_power7,FXU_power7,nothing*3,FXU_power7")
@@ -228,12 +228,14 @@ (define_bypass 5 "power8-fast-compare,power8-compare"
"power8-crlogical,power8-mfcr,power8-mfcrf,power8-branch")
(define_insn_reservation "power8-mul" 4
- (and (eq_attr "type" "imul,imul2,imul3,lmul")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "no")
(eq_attr "cpu" "power8"))
"DU_any_power8,FXU_power8")
(define_insn_reservation "power8-mul-compare" 4
- (and (eq_attr "type" "imul_compare,lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes")
(eq_attr "cpu" "power8"))
"DU_cracked_power8,FXU_power8")
@@ -26188,12 +26188,15 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
case TYPE_CMP:
case TYPE_COMPARE:
case TYPE_DELAYED_COMPARE:
- case TYPE_IMUL_COMPARE:
- case TYPE_LMUL_COMPARE:
case TYPE_FPCOMPARE:
case TYPE_CR_LOGICAL:
case TYPE_DELAYED_CR:
return cost + 2;
+ case TYPE_MUL:
+ if (get_attr_dot (dep_insn) == DOT_YES)
+ return cost + 2;
+ else
+ break;
default:
break;
}
@@ -26252,12 +26255,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
return 3;
break;
}
- case TYPE_IMUL:
- case TYPE_IMUL2:
- case TYPE_IMUL3:
- case TYPE_LMUL:
- case TYPE_IMUL_COMPARE:
- case TYPE_LMUL_COMPARE:
+ case TYPE_MUL:
{
if (! store_data_bypass_p (dep_insn, insn))
return 17;
@@ -26328,12 +26326,7 @@ rs6000_adjust_cost (rtx insn, rtx link, rtx dep_insn, int cost)
return 3;
break;
}
- case TYPE_IMUL:
- case TYPE_IMUL2:
- case TYPE_IMUL3:
- case TYPE_LMUL:
- case TYPE_IMUL_COMPARE:
- case TYPE_LMUL_COMPARE:
+ case TYPE_MUL:
{
if (set_to_load_agen (dep_insn, insn))
return 17;
@@ -26498,7 +26491,8 @@ is_cracked_insn (rtx insn)
&& get_attr_update (insn) == UPDATE_YES)
|| type == TYPE_DELAYED_CR
|| type == TYPE_COMPARE || type == TYPE_DELAYED_COMPARE
- || type == TYPE_IMUL_COMPARE || type == TYPE_LMUL_COMPARE
+ || (type == TYPE_MUL
+ && get_attr_dot (insn) == DOT_YES)
|| type == TYPE_IDIV || type == TYPE_LDIV
|| type == TYPE_INSERT_WORD)
return true;
@@ -26654,7 +26648,7 @@ rs6000_adjust_priority (rtx insn ATTRIBUTE_UNUSED, int priority)
default:
break;
- case TYPE_IMUL:
+ case TYPE_MUL:
case TYPE_IDIV:
fprintf (stderr, "priority was %#x (%d) before adjustment\n",
priority, priority);
@@ -26708,10 +26702,7 @@ is_nonpipeline_insn (rtx insn)
return false;
type = get_attr_type (insn);
- if (type == TYPE_IMUL
- || type == TYPE_IMUL2
- || type == TYPE_IMUL3
- || type == TYPE_LMUL
+ if (type == TYPE_MUL
|| type == TYPE_IDIV
|| type == TYPE_LDIV
|| type == TYPE_SDIV
@@ -27334,15 +27325,10 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_SHIFT:
case TYPE_VAR_SHIFT_ROTATE:
case TYPE_TRAP:
- case TYPE_IMUL:
- case TYPE_IMUL2:
- case TYPE_IMUL3:
- case TYPE_LMUL:
+ case TYPE_MUL:
case TYPE_IDIV:
case TYPE_INSERT_WORD:
case TYPE_DELAYED_COMPARE:
- case TYPE_IMUL_COMPARE:
- case TYPE_LMUL_COMPARE:
case TYPE_FPCOMPARE:
case TYPE_MFCR:
case TYPE_MTCR:
@@ -27385,6 +27371,11 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_MFJMPR:
case TYPE_MTJMPR:
return true;
+ case TYPE_MUL:
+ if (get_attr_dot (insn) == DOT_YES)
+ return true;
+ else
+ break;
case TYPE_LOAD:
if (get_attr_sign_extend (insn) == SIGN_EXTEND_YES
|| get_attr_update (insn) == UPDATE_YES)
@@ -27415,8 +27406,6 @@ insn_must_be_first_in_group (rtx insn)
case TYPE_COMPARE:
case TYPE_DELAYED_COMPARE:
case TYPE_VAR_DELAYED_COMPARE:
- case TYPE_IMUL_COMPARE:
- case TYPE_LMUL_COMPARE:
case TYPE_SYNC:
case TYPE_ISYNC:
case TYPE_LOAD_L:
@@ -27480,14 +27469,9 @@ insn_must_be_last_in_group (rtx insn)
case TYPE_SHIFT:
case TYPE_VAR_SHIFT_ROTATE:
case TYPE_TRAP:
- case TYPE_IMUL:
- case TYPE_IMUL2:
- case TYPE_IMUL3:
- case TYPE_LMUL:
+ case TYPE_MUL:
case TYPE_IDIV:
case TYPE_DELAYED_COMPARE:
- case TYPE_IMUL_COMPARE:
- case TYPE_LMUL_COMPARE:
case TYPE_FPCOMPARE:
case TYPE_MFCR:
case TYPE_MTCR:
@@ -160,13 +160,12 @@ (define_c_enum "unspecv"
(define_attr "type"
"integer,two,three,
shift,var_shift_rotate,insert_word,insert_dword,
- imul,imul2,imul3,lmul,halfmul,idiv,ldiv,
+ mul,halfmul,idiv,ldiv,
exts,cntlz,popcnt,isel,
load,store,fpload,fpstore,vecload,vecstore,
cmp,
branch,jmpreg,mfjmpr,mtjmpr,trap,isync,sync,load_l,store_c,
compare,fast_compare,delayed_compare,var_delayed_compare,
- imul_compare,lmul_compare,
cr_logical,delayed_cr,mfcr,mfcrf,mtcr,
fpcompare,fp,fpsimple,dmul,sdiv,ddiv,ssqrt,dsqrt,
brinc,
@@ -175,6 +174,14 @@ (define_attr "type"
htm"
(const_string "integer"))
+;; What data size does this instruction work on?
+;; This is used for mul.
+(define_attr "size" "8,16,32,64" (const_string "32"))
+
+;; Is this instruction record form ("dot", signed compare to 0, writing CR0)?
+;; This is used for mul.
+(define_attr "dot" "no,yes" (const_string "no"))
+
;; Does this instruction sign-extend its result?
;; This is used for load insns.
(define_attr "sign_extend" "no,yes" (const_string "no"))
@@ -229,7 +236,9 @@ (define_attr "cpu"
;; If this instruction is microcoded on the CELL processor
; The default for load extended, the recorded instructions and rotate/shifts by a variable is always microcoded
(define_attr "cell_micro" "not,conditional,always"
- (if_then_else (ior (eq_attr "type" "compare,delayed_compare,imul_compare,lmul_compare,var_shift_rotate,var_delayed_compare")
+ (if_then_else (ior (eq_attr "type" "compare,delayed_compare,var_shift_rotate,var_delayed_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "dot" "yes"))
(and (eq_attr "type" "load")
(eq_attr "sign_extend" "yes")))
(const_string "always")
@@ -2665,12 +2674,13 @@ (define_insn "mulsi3"
"@
mullw %0,%1,%2
mulli %0,%1,%2"
- [(set (attr "type")
+ [(set_attr "type" "mul")
+ (set (attr "size")
(cond [(match_operand:SI 2 "s8bit_cint_operand" "")
- (const_string "imul3")
+ (const_string "8")
(match_operand:SI 2 "short_cint_operand" "")
- (const_string "imul2")]
- (const_string "imul")))])
+ (const_string "16")]
+ (const_string "32")))])
(define_insn "*mulsi3_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -2682,7 +2692,8 @@ (define_insn "*mulsi3_internal1"
"@
mullw. %3,%1,%2
#"
- [(set_attr "type" "imul_compare")
+ [(set_attr "type" "mul")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -2710,7 +2721,8 @@ (define_insn "*mulsi3_internal2"
"@
mullw. %0,%1,%2
#"
- [(set_attr "type" "imul_compare")
+ [(set_attr "type" "mul")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -6600,7 +6612,7 @@ (define_insn "mulsidi3"
? \"mulhw %0,%1,%2\;mullw %L0,%1,%2\"
: \"mulhw %L0,%1,%2\;mullw %0,%1,%2\";
}
- [(set_attr "type" "imul")
+ [(set_attr "type" "mul")
(set_attr "length" "8")])
(define_split
@@ -6634,7 +6646,7 @@ (define_insn "umulsidi3"
? \"mulhwu %0,%1,%2\;mullw %L0,%1,%2\"
: \"mulhwu %L0,%1,%2\;mullw %0,%1,%2\";
}"
- [(set_attr "type" "imul")
+ [(set_attr "type" "mul")
(set_attr "length" "8")])
(define_split
@@ -6667,7 +6679,7 @@ (define_insn "smulsi3_highpart"
(const_int 32))))]
""
"mulhw %0,%1,%2"
- [(set_attr "type" "imul")])
+ [(set_attr "type" "mul")])
(define_insn "umulsi3_highpart"
[(set (match_operand:SI 0 "gpc_reg_operand" "=r")
@@ -6679,7 +6691,7 @@ (define_insn "umulsi3_highpart"
(const_int 32))))]
""
"mulhwu %0,%1,%2"
- [(set_attr "type" "imul")])
+ [(set_attr "type" "mul")])
;; Shift by a variable amount is too complex to be worth open-coding. We
;; just handle shifts by constants.
@@ -6734,12 +6746,13 @@ (define_insn "muldi3"
"@
mulld %0,%1,%2
mulli %0,%1,%2"
- [(set (attr "type")
+ [(set_attr "type" "mul")
+ (set (attr "size")
(cond [(match_operand:SI 2 "s8bit_cint_operand" "")
- (const_string "imul3")
+ (const_string "8")
(match_operand:SI 2 "short_cint_operand" "")
- (const_string "imul2")]
- (const_string "lmul")))])
+ (const_string "16")]
+ (const_string "64")))])
(define_insn "*muldi3_internal1"
[(set (match_operand:CC 0 "cc_reg_operand" "=x,?y")
@@ -6751,7 +6764,9 @@ (define_insn "*muldi3_internal1"
"@
mulld. %3,%1,%2
#"
- [(set_attr "type" "lmul_compare")
+ [(set_attr "type" "mul")
+ (set_attr "size" "64")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -6779,7 +6794,9 @@ (define_insn "*muldi3_internal2"
"@
mulld. %0,%1,%2
#"
- [(set_attr "type" "lmul_compare")
+ [(set_attr "type" "mul")
+ (set_attr "size" "64")
+ (set_attr "dot" "yes")
(set_attr "length" "4,8")])
(define_split
@@ -6807,7 +6824,8 @@ (define_insn "smuldi3_highpart"
(const_int 64))))]
"TARGET_POWERPC64"
"mulhd %0,%1,%2"
- [(set_attr "type" "lmul")])
+ [(set_attr "type" "mul")
+ (set_attr "size" "64")])
(define_insn "umuldi3_highpart"
[(set (match_operand:DI 0 "gpc_reg_operand" "=r")
@@ -6819,7 +6837,8 @@ (define_insn "umuldi3_highpart"
(const_int 64))))]
"TARGET_POWERPC64"
"mulhdu %0,%1,%2"
- [(set_attr "type" "lmul")])
+ [(set_attr "type" "mul")
+ (set_attr "size" "64")])
(define_expand "mulditi3"
[(set (match_operand:TI 0 "gpc_reg_operand")
@@ -62,22 +62,26 @@ (define_insn_reservation "rs64a-three" 1
"iu_rs64,iu_rs64,iu_rs64")
(define_insn_reservation "rs64a-imul" 20
- (and (eq_attr "type" "imul,imul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "32")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*13")
(define_insn_reservation "rs64a-imul2" 12
- (and (eq_attr "type" "imul2")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "16")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*5")
(define_insn_reservation "rs64a-imul3" 8
- (and (eq_attr "type" "imul3")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "8")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*2")
(define_insn_reservation "rs64a-lmul" 34
- (and (eq_attr "type" "lmul,lmul_compare")
+ (and (eq_attr "type" "mul")
+ (eq_attr "size" "64")
(eq_attr "cpu" "rs64a"))
"mciu_rs64*34")
@@ -39,7 +39,7 @@ (define_insn_reservation "titan_fxu_adder" 1
"titan_issue,titan_fxu_sh")
(define_insn_reservation "titan_imul" 5
- (and (eq_attr "type" "imul,imul2,imul3,imul_compare")
+ (and (eq_attr "type" "mul")
(eq_attr "cpu" "titan"))
"titan_issue,titan_fxu_sh,nothing*5,titan_fxu_wb")