Message ID | 20240517145302.971019-1-cleger@rivosinc.com |
---|---|
Headers | show |
Series | Add support for a few Zc* extensions, Zcmop and Zimop | expand |
On Fri, May 17, 2024 at 8:23 PM Clément Léger <cleger@rivosinc.com> wrote: > > Extend the KVM ISA extension ONE_REG interface to allow KVM user space > to detect and enable Zimop extension for Guest/VM. > > Signed-off-by: Clément Léger <cleger@rivosinc.com> LGTM. Reviewed-by: Anup Patel <anup@brainfault.org> Acked-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > arch/riscv/include/uapi/asm/kvm.h | 1 + > arch/riscv/kvm/vcpu_onereg.c | 2 ++ > 2 files changed, 3 insertions(+) > > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h > index b1c503c2959c..35a12aa1953e 100644 > --- a/arch/riscv/include/uapi/asm/kvm.h > +++ b/arch/riscv/include/uapi/asm/kvm.h > @@ -167,6 +167,7 @@ enum KVM_RISCV_ISA_EXT_ID { > KVM_RISCV_ISA_EXT_ZFA, > KVM_RISCV_ISA_EXT_ZTSO, > KVM_RISCV_ISA_EXT_ZACAS, > + KVM_RISCV_ISA_EXT_ZIMOP, > KVM_RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c > index f4a6124d25c9..c6ee763422f2 100644 > --- a/arch/riscv/kvm/vcpu_onereg.c > +++ b/arch/riscv/kvm/vcpu_onereg.c > @@ -60,6 +60,7 @@ static const unsigned long kvm_isa_ext_arr[] = { > KVM_ISA_EXT_ARR(ZIHINTNTL), > KVM_ISA_EXT_ARR(ZIHINTPAUSE), > KVM_ISA_EXT_ARR(ZIHPM), > + KVM_ISA_EXT_ARR(ZIMOP), > KVM_ISA_EXT_ARR(ZKND), > KVM_ISA_EXT_ARR(ZKNE), > KVM_ISA_EXT_ARR(ZKNH), > @@ -137,6 +138,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) > case KVM_RISCV_ISA_EXT_ZIHINTNTL: > case KVM_RISCV_ISA_EXT_ZIHINTPAUSE: > case KVM_RISCV_ISA_EXT_ZIHPM: > + case KVM_RISCV_ISA_EXT_ZIMOP: > case KVM_RISCV_ISA_EXT_ZKND: > case KVM_RISCV_ISA_EXT_ZKNE: > case KVM_RISCV_ISA_EXT_ZKNH: > -- > 2.43.0 >
On Fri, May 17, 2024 at 8:23 PM Clément Léger <cleger@rivosinc.com> wrote: > > The KVM RISC-V allows Zimop extension for Guest/VM so add this > extension to get-reg-list test. > > Signed-off-by: Clément Léger <cleger@rivosinc.com> LGTM. Reviewed-by: Anup Patel <anup@brainfault.org> Acked-by: Anup Patel <anup@brainfault.org> Regards, Anup > --- > tools/testing/selftests/kvm/riscv/get-reg-list.c | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/tools/testing/selftests/kvm/riscv/get-reg-list.c b/tools/testing/selftests/kvm/riscv/get-reg-list.c > index b882b7b9b785..40107bb61975 100644 > --- a/tools/testing/selftests/kvm/riscv/get-reg-list.c > +++ b/tools/testing/selftests/kvm/riscv/get-reg-list.c > @@ -67,6 +67,7 @@ bool filter_reg(__u64 reg) > case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTNTL: > case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHINTPAUSE: > case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIHPM: > + case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZIMOP: > case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKND: > case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNE: > case KVM_REG_RISCV_ISA_EXT | KVM_REG_RISCV_ISA_SINGLE | KVM_RISCV_ISA_EXT_ZKNH: > @@ -432,6 +433,7 @@ static const char *isa_ext_single_id_to_str(__u64 reg_off) > KVM_ISA_EXT_ARR(ZIHINTNTL), > KVM_ISA_EXT_ARR(ZIHINTPAUSE), > KVM_ISA_EXT_ARR(ZIHPM), > + KVM_ISA_EXT_ARR(ZIMOP), > KVM_ISA_EXT_ARR(ZKND), > KVM_ISA_EXT_ARR(ZKNE), > KVM_ISA_EXT_ARR(ZKNH), > @@ -955,6 +957,7 @@ KVM_ISA_EXT_SIMPLE_CONFIG(zifencei, ZIFENCEI); > KVM_ISA_EXT_SIMPLE_CONFIG(zihintntl, ZIHINTNTL); > KVM_ISA_EXT_SIMPLE_CONFIG(zihintpause, ZIHINTPAUSE); > KVM_ISA_EXT_SIMPLE_CONFIG(zihpm, ZIHPM); > +KVM_ISA_EXT_SIMPLE_CONFIG(zimop, ZIMOP); > KVM_ISA_EXT_SIMPLE_CONFIG(zknd, ZKND); > KVM_ISA_EXT_SIMPLE_CONFIG(zkne, ZKNE); > KVM_ISA_EXT_SIMPLE_CONFIG(zknh, ZKNH); > @@ -1010,6 +1013,7 @@ struct vcpu_reg_list *vcpu_configs[] = { > &config_zihintntl, > &config_zihintpause, > &config_zihpm, > + &config_zimop, > &config_zknd, > &config_zkne, > &config_zknh, > -- > 2.43.0 >
On Fri, May 17, 2024 at 04:52:47PM +0200, Clément Léger wrote: > Since a few extensions (Zicbom/Zicboz) already needs validation and > future ones will need it as well (Zc*) add a validate() callback to > struct riscv_isa_ext_data. This require to rework the way extensions are > parsed and split it in two phases. First phase is isa string or isa > extension list parsing and consists in enabling all the extensions in a > temporary bitmask (source isa) without any validation. The second step > "resolves" the final isa bitmap, handling potential missing dependencies. > The mechanism is quite simple and simply validate each extension > described in the source bitmap before enabling it in the resolved isa > bitmap. validate() callbacks can return either 0 for success, > -EPROBEDEFER if extension needs to be validated again at next loop. A > previous ISA bitmap is kept to avoid looping multiple times if an > extension dependencies are never satisfied until we reach a stable > state. In order to avoid any potential infinite looping, allow looping > a maximum of the number of extension we handle. Zicboz and Zicbom > extensions are modified to use this validation mechanism. I wish we weren't doin' it at all, but since we have to, I think what you've got here is good. Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Do you want me to send some patches for the F/V stuff we discussed previously? Cheers, Conor.
On 17/05/2024 18:44, Conor Dooley wrote: > On Fri, May 17, 2024 at 04:52:47PM +0200, Clément Léger wrote: >> Since a few extensions (Zicbom/Zicboz) already needs validation and >> future ones will need it as well (Zc*) add a validate() callback to >> struct riscv_isa_ext_data. This require to rework the way extensions are >> parsed and split it in two phases. First phase is isa string or isa >> extension list parsing and consists in enabling all the extensions in a >> temporary bitmask (source isa) without any validation. The second step >> "resolves" the final isa bitmap, handling potential missing dependencies. >> The mechanism is quite simple and simply validate each extension >> described in the source bitmap before enabling it in the resolved isa >> bitmap. validate() callbacks can return either 0 for success, >> -EPROBEDEFER if extension needs to be validated again at next loop. A >> previous ISA bitmap is kept to avoid looping multiple times if an >> extension dependencies are never satisfied until we reach a stable >> state. In order to avoid any potential infinite looping, allow looping >> a maximum of the number of extension we handle. Zicboz and Zicbom >> extensions are modified to use this validation mechanism. > > I wish we weren't doin' it at all, but since we have to, I think what > you've got here is good. Yup, this is what you got with a fast evolving architecture I guess ;) > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Do you want me to send some patches for the F/V stuff we discussed > previously? Sure go ahead, I did not have anything written yet. Thanks, Clément > > Cheers, > Conor.
On Fri, May 17, 2024 at 04:52:48PM +0200, Clément Léger wrote: > +static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, > + const unsigned long *isa_bitmap) > +{ > + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) ? 0 : -EPROBE_DEFER; > +} > +static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data, > + const unsigned long *isa_bitmap) > +{ > + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && > + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d) ? 0 : -EPROBE_DEFER; > +} Could you write the logic in these out normally please? I think they'd be more understandable (particular this second one) broken down and with early return. Otherwise, Reviewed-by: Conor Dooley <conor.dooley@microchip.com> Cheers, Conor.
On 21/05/2024 21:49, Conor Dooley wrote: > On Fri, May 17, 2024 at 04:52:48PM +0200, Clément Léger wrote: > >> +static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, >> + const unsigned long *isa_bitmap) >> +{ >> + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) ? 0 : -EPROBE_DEFER; >> +} >> +static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data, >> + const unsigned long *isa_bitmap) >> +{ >> + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && >> + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d) ? 0 : -EPROBE_DEFER; >> +} > > Could you write the logic in these out normally please? I think they'd > be more understandable (particular this second one) broken down and with > early return. Yes sure. I'll probably make the same thing for zcf_validate as well as removing the #ifdef and using IS_ENABLED(): static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data, const unsigned long *isa_bitmap) { if (IS_ENABLED(CONFIG_64BIT)) return -EINVAL; if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) return 0; return -EPROBE_DEFER; } > > Otherwise, > Reviewed-by: Conor Dooley <conor.dooley@microchip.com> > > Cheers, > Conor.
On Fri, May 17, 2024 at 04:52:42PM +0200, Clément Léger wrote: > Add parsing for Zimop ISA extension which was ratified in commit > 58220614a5f of the riscv-isa-manual. > > Signed-off-by: Clément Léger <cleger@rivosinc.com> > --- > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index 1f2d2599c655..b1896dade74c 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -80,6 +80,7 @@ > #define RISCV_ISA_EXT_ZFA 71 > #define RISCV_ISA_EXT_ZTSO 72 > #define RISCV_ISA_EXT_ZACAS 73 > +#define RISCV_ISA_EXT_ZIMOP 74 Since my changes for removing xandespmu haven't landed here yet I think you should keep RISCV_ISA_EXT_XANDESPMU in the diff here and make RISCV_ISA_EXT_ZIMOP have a key of 75. Palmer can probably resolve the conflicting keys when these two series are merged. - Charlie > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 2993318b8ea2..41f8ae22e7a0 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -241,6 +241,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), > __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), > + __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP), > __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), > __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), > __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), > -- > 2.43.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Fri, May 17, 2024 at 04:52:43PM +0200, Clément Léger wrote: > Export Zimop ISA extension through hwprobe. > > Signed-off-by: Clément Léger <cleger@rivosinc.com> > --- > Documentation/arch/riscv/hwprobe.rst | 4 ++++ > arch/riscv/include/uapi/asm/hwprobe.h | 1 + > arch/riscv/kernel/sys_hwprobe.c | 1 + > 3 files changed, 6 insertions(+) > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > index 204cd4433af5..48be38e0b788 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -192,6 +192,10 @@ The following keys are defined: > supported as defined in the RISC-V ISA manual starting from commit > d8ab5c78c207 ("Zihintpause is ratified"). > > + * :c:macro:`RISCV_HWPROBE_EXT_ZIMOP`: The Zimop May-Be-Operations extension is > + supported as defined in the RISC-V ISA manual starting from commit > + 58220614a5f ("Zimop is ratified/1.0"). > + > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > information about the selected set of processors. > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 31c570cbd1c5..3b16a12204b1 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -60,6 +60,7 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_EXT_ZACAS (1ULL << 34) > #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) > #define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36) > +#define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 37) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > index 969ef3d59dbe..fc6f4238f0b3 100644 > --- a/arch/riscv/kernel/sys_hwprobe.c > +++ b/arch/riscv/kernel/sys_hwprobe.c > @@ -112,6 +112,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > EXT_KEY(ZACAS); > EXT_KEY(ZICOND); > EXT_KEY(ZIHINTPAUSE); > + EXT_KEY(ZIMOP); > > if (has_vector()) { > EXT_KEY(ZVBB); > -- > 2.43.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
On Fri, May 17, 2024 at 04:52:44PM +0200, Clément Léger wrote: > Extend the KVM ISA extension ONE_REG interface to allow KVM user space > to detect and enable Zimop extension for Guest/VM. > > Signed-off-by: Clément Léger <cleger@rivosinc.com> > --- > arch/riscv/include/uapi/asm/kvm.h | 1 + > arch/riscv/kvm/vcpu_onereg.c | 2 ++ > 2 files changed, 3 insertions(+) > > diff --git a/arch/riscv/include/uapi/asm/kvm.h b/arch/riscv/include/uapi/asm/kvm.h > index b1c503c2959c..35a12aa1953e 100644 > --- a/arch/riscv/include/uapi/asm/kvm.h > +++ b/arch/riscv/include/uapi/asm/kvm.h > @@ -167,6 +167,7 @@ enum KVM_RISCV_ISA_EXT_ID { > KVM_RISCV_ISA_EXT_ZFA, > KVM_RISCV_ISA_EXT_ZTSO, > KVM_RISCV_ISA_EXT_ZACAS, KVM_RISCV_ISA_EXT_SSCOFPMF got added here in 6.10-rc1 so there is a conflict now unfortunately. Easy to fix at least! - Charlie > + KVM_RISCV_ISA_EXT_ZIMOP, > KVM_RISCV_ISA_EXT_MAX, > }; > > diff --git a/arch/riscv/kvm/vcpu_onereg.c b/arch/riscv/kvm/vcpu_onereg.c > index f4a6124d25c9..c6ee763422f2 100644 > --- a/arch/riscv/kvm/vcpu_onereg.c > +++ b/arch/riscv/kvm/vcpu_onereg.c > @@ -60,6 +60,7 @@ static const unsigned long kvm_isa_ext_arr[] = { > KVM_ISA_EXT_ARR(ZIHINTNTL), > KVM_ISA_EXT_ARR(ZIHINTPAUSE), > KVM_ISA_EXT_ARR(ZIHPM), > + KVM_ISA_EXT_ARR(ZIMOP), > KVM_ISA_EXT_ARR(ZKND), > KVM_ISA_EXT_ARR(ZKNE), > KVM_ISA_EXT_ARR(ZKNH), > @@ -137,6 +138,7 @@ static bool kvm_riscv_vcpu_isa_disable_allowed(unsigned long ext) > case KVM_RISCV_ISA_EXT_ZIHINTNTL: > case KVM_RISCV_ISA_EXT_ZIHINTPAUSE: > case KVM_RISCV_ISA_EXT_ZIHPM: > + case KVM_RISCV_ISA_EXT_ZIMOP: > case KVM_RISCV_ISA_EXT_ZKND: > case KVM_RISCV_ISA_EXT_ZKNE: > case KVM_RISCV_ISA_EXT_ZKNH: > -- > 2.43.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv
On Wed, May 29, 2024 at 03:08:39PM -0700, Charlie Jenkins wrote: > On Fri, May 17, 2024 at 04:52:42PM +0200, Clément Léger wrote: > > Add parsing for Zimop ISA extension which was ratified in commit > > 58220614a5f of the riscv-isa-manual. > > > > Signed-off-by: Clément Léger <cleger@rivosinc.com> > > --- > > arch/riscv/include/asm/hwcap.h | 1 + > > arch/riscv/kernel/cpufeature.c | 1 + > > 2 files changed, 2 insertions(+) > > > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > > index 1f2d2599c655..b1896dade74c 100644 > > --- a/arch/riscv/include/asm/hwcap.h > > +++ b/arch/riscv/include/asm/hwcap.h > > @@ -80,6 +80,7 @@ > > #define RISCV_ISA_EXT_ZFA 71 > > #define RISCV_ISA_EXT_ZTSO 72 > > #define RISCV_ISA_EXT_ZACAS 73 > > +#define RISCV_ISA_EXT_ZIMOP 74 > > Since my changes for removing xandespmu haven't landed here yet I think > you should keep RISCV_ISA_EXT_XANDESPMU in the diff here and make > RISCV_ISA_EXT_ZIMOP have a key of 75. Palmer can probably resolve the > conflicting keys when these two series are merged. > > - Charlie I missed that other patches in this series were based off my xtheadvector changes. It's not in the cover letter that there is a dependency though. What do you need from that series for this series to work? - Charlie > > > > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > > index 2993318b8ea2..41f8ae22e7a0 100644 > > --- a/arch/riscv/kernel/cpufeature.c > > +++ b/arch/riscv/kernel/cpufeature.c > > @@ -241,6 +241,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > > __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), > > __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > > __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), > > + __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP), > > __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), > > __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), > > __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), > > -- > > 2.43.0 > > > > > > _______________________________________________ > > linux-riscv mailing list > > linux-riscv@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-riscv >
On 30/05/2024 00:21, Charlie Jenkins wrote: > On Wed, May 29, 2024 at 03:08:39PM -0700, Charlie Jenkins wrote: >> On Fri, May 17, 2024 at 04:52:42PM +0200, Clément Léger wrote: >>> Add parsing for Zimop ISA extension which was ratified in commit >>> 58220614a5f of the riscv-isa-manual. >>> >>> Signed-off-by: Clément Léger <cleger@rivosinc.com> >>> --- >>> arch/riscv/include/asm/hwcap.h | 1 + >>> arch/riscv/kernel/cpufeature.c | 1 + >>> 2 files changed, 2 insertions(+) >>> >>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >>> index 1f2d2599c655..b1896dade74c 100644 >>> --- a/arch/riscv/include/asm/hwcap.h >>> +++ b/arch/riscv/include/asm/hwcap.h >>> @@ -80,6 +80,7 @@ >>> #define RISCV_ISA_EXT_ZFA 71 >>> #define RISCV_ISA_EXT_ZTSO 72 >>> #define RISCV_ISA_EXT_ZACAS 73 >>> +#define RISCV_ISA_EXT_ZIMOP 74 >> >> Since my changes for removing xandespmu haven't landed here yet I think >> you should keep RISCV_ISA_EXT_XANDESPMU in the diff here and make >> RISCV_ISA_EXT_ZIMOP have a key of 75. Palmer can probably resolve the >> conflicting keys when these two series are merged. >> >> - Charlie > > I missed that other patches in this series were based off my > xtheadvector changes. It's not in the cover letter that there is a > dependency though. What do you need from that series for this series to > work? Hey Charlie, I'm not based directly on any of your series, but on riscv/for-next which probably already contains your patches. Clément > > - Charlie > >> >>> >>> #define RISCV_ISA_EXT_XLINUXENVCFG 127 >>> >>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >>> index 2993318b8ea2..41f8ae22e7a0 100644 >>> --- a/arch/riscv/kernel/cpufeature.c >>> +++ b/arch/riscv/kernel/cpufeature.c >>> @@ -241,6 +241,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { >>> __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), >>> __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), >>> __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), >>> + __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP), >>> __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), >>> __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), >>> __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), >>> -- >>> 2.43.0 >>> >>> >>> _______________________________________________ >>> linux-riscv mailing list >>> linux-riscv@lists.infradead.org >>> http://lists.infradead.org/mailman/listinfo/linux-riscv >>
On Thu, May 30, 2024 at 10:12:39AM +0200, Clément Léger wrote: > > > On 30/05/2024 00:21, Charlie Jenkins wrote: > > On Wed, May 29, 2024 at 03:08:39PM -0700, Charlie Jenkins wrote: > >> On Fri, May 17, 2024 at 04:52:42PM +0200, Clément Léger wrote: > >>> Add parsing for Zimop ISA extension which was ratified in commit > >>> 58220614a5f of the riscv-isa-manual. > >>> > >>> Signed-off-by: Clément Léger <cleger@rivosinc.com> > >>> --- > >>> arch/riscv/include/asm/hwcap.h | 1 + > >>> arch/riscv/kernel/cpufeature.c | 1 + > >>> 2 files changed, 2 insertions(+) > >>> > >>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > >>> index 1f2d2599c655..b1896dade74c 100644 > >>> --- a/arch/riscv/include/asm/hwcap.h > >>> +++ b/arch/riscv/include/asm/hwcap.h > >>> @@ -80,6 +80,7 @@ > >>> #define RISCV_ISA_EXT_ZFA 71 > >>> #define RISCV_ISA_EXT_ZTSO 72 > >>> #define RISCV_ISA_EXT_ZACAS 73 > >>> +#define RISCV_ISA_EXT_ZIMOP 74 > >> > >> Since my changes for removing xandespmu haven't landed here yet I think > >> you should keep RISCV_ISA_EXT_XANDESPMU in the diff here and make > >> RISCV_ISA_EXT_ZIMOP have a key of 75. Palmer can probably resolve the > >> conflicting keys when these two series are merged. > >> > >> - Charlie > > > > I missed that other patches in this series were based off my > > xtheadvector changes. It's not in the cover letter that there is a > > dependency though. What do you need from that series for this series to > > work? > > Hey Charlie, I'm not based directly on any of your series, but on > riscv/for-next which probably already contains your patches. > > Clément There was some churn here so I didn't expect those to be merged, it looks like a subset of the patches were added to riscv/for-next, sorry for the confusion! Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> > > > > > - Charlie > > > >> > >>> > >>> #define RISCV_ISA_EXT_XLINUXENVCFG 127 > >>> > >>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > >>> index 2993318b8ea2..41f8ae22e7a0 100644 > >>> --- a/arch/riscv/kernel/cpufeature.c > >>> +++ b/arch/riscv/kernel/cpufeature.c > >>> @@ -241,6 +241,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > >>> __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), > >>> __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), > >>> __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), > >>> + __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP), > >>> __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), > >>> __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), > >>> __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), > >>> -- > >>> 2.43.0 > >>> > >>> > >>> _______________________________________________ > >>> linux-riscv mailing list > >>> linux-riscv@lists.infradead.org > >>> http://lists.infradead.org/mailman/listinfo/linux-riscv > >>
On 30/05/2024 16:37, Charlie Jenkins wrote: > On Thu, May 30, 2024 at 10:12:39AM +0200, Clément Léger wrote: >> >> >> On 30/05/2024 00:21, Charlie Jenkins wrote: >>> On Wed, May 29, 2024 at 03:08:39PM -0700, Charlie Jenkins wrote: >>>> On Fri, May 17, 2024 at 04:52:42PM +0200, Clément Léger wrote: >>>>> Add parsing for Zimop ISA extension which was ratified in commit >>>>> 58220614a5f of the riscv-isa-manual. >>>>> >>>>> Signed-off-by: Clément Léger <cleger@rivosinc.com> >>>>> --- >>>>> arch/riscv/include/asm/hwcap.h | 1 + >>>>> arch/riscv/kernel/cpufeature.c | 1 + >>>>> 2 files changed, 2 insertions(+) >>>>> >>>>> diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h >>>>> index 1f2d2599c655..b1896dade74c 100644 >>>>> --- a/arch/riscv/include/asm/hwcap.h >>>>> +++ b/arch/riscv/include/asm/hwcap.h >>>>> @@ -80,6 +80,7 @@ >>>>> #define RISCV_ISA_EXT_ZFA 71 >>>>> #define RISCV_ISA_EXT_ZTSO 72 >>>>> #define RISCV_ISA_EXT_ZACAS 73 >>>>> +#define RISCV_ISA_EXT_ZIMOP 74 >>>> >>>> Since my changes for removing xandespmu haven't landed here yet I think >>>> you should keep RISCV_ISA_EXT_XANDESPMU in the diff here and make >>>> RISCV_ISA_EXT_ZIMOP have a key of 75. Palmer can probably resolve the >>>> conflicting keys when these two series are merged. >>>> >>>> - Charlie >>> >>> I missed that other patches in this series were based off my >>> xtheadvector changes. It's not in the cover letter that there is a >>> dependency though. What do you need from that series for this series to >>> work? >> >> Hey Charlie, I'm not based directly on any of your series, but on >> riscv/for-next which probably already contains your patches. >> >> Clément > > There was some churn here so I didn't expect those to be merged, it > looks like a subset of the patches were added to riscv/for-next, sorry > for the confusion! No worries, it seems strange indeed that some of them were merged but not the other :/ > > Reviewed-by: Charlie Jenkins <charlie@rivosinc.com> Thanks ! > >> >>> >>> - Charlie >>> >>>> >>>>> >>>>> #define RISCV_ISA_EXT_XLINUXENVCFG 127 >>>>> >>>>> diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c >>>>> index 2993318b8ea2..41f8ae22e7a0 100644 >>>>> --- a/arch/riscv/kernel/cpufeature.c >>>>> +++ b/arch/riscv/kernel/cpufeature.c >>>>> @@ -241,6 +241,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { >>>>> __RISCV_ISA_EXT_DATA(zihintntl, RISCV_ISA_EXT_ZIHINTNTL), >>>>> __RISCV_ISA_EXT_DATA(zihintpause, RISCV_ISA_EXT_ZIHINTPAUSE), >>>>> __RISCV_ISA_EXT_DATA(zihpm, RISCV_ISA_EXT_ZIHPM), >>>>> + __RISCV_ISA_EXT_DATA(zimop, RISCV_ISA_EXT_ZIMOP), >>>>> __RISCV_ISA_EXT_DATA(zacas, RISCV_ISA_EXT_ZACAS), >>>>> __RISCV_ISA_EXT_DATA(zfa, RISCV_ISA_EXT_ZFA), >>>>> __RISCV_ISA_EXT_DATA(zfh, RISCV_ISA_EXT_ZFH), >>>>> -- >>>>> 2.43.0 >>>>> >>>>> >>>>> _______________________________________________ >>>>> linux-riscv mailing list >>>>> linux-riscv@lists.infradead.org >>>>> http://lists.infradead.org/mailman/listinfo/linux-riscv >>>>
On Fri, May 17, 2024 at 04:52:49PM +0200, Clément Léger wrote: > Export Zca, Zcf, Zcd and Zcb ISA extension through hwprobe. > > Signed-off-by: Clément Léger <cleger@rivosinc.com> > --- > Documentation/arch/riscv/hwprobe.rst | 20 ++++++++++++++++++++ > arch/riscv/include/uapi/asm/hwprobe.h | 4 ++++ > arch/riscv/kernel/sys_hwprobe.c | 4 ++++ > 3 files changed, 28 insertions(+) > > diff --git a/Documentation/arch/riscv/hwprobe.rst b/Documentation/arch/riscv/hwprobe.rst > index 48be38e0b788..cad84f51412d 100644 > --- a/Documentation/arch/riscv/hwprobe.rst > +++ b/Documentation/arch/riscv/hwprobe.rst > @@ -196,6 +196,26 @@ The following keys are defined: > supported as defined in the RISC-V ISA manual starting from commit > 58220614a5f ("Zimop is ratified/1.0"). > > + * :c:macro:`RISCV_HWPROBE_EXT_ZCA`: The Zca extension part of Zc* standard > + extensions for code size reduction, as ratified in commit 8be3419c1c0 > + ("Zcf doesn't exist on RV64 as it contains no instructions") of > + riscv-code-size-reduction. > + > + * :c:macro:`RISCV_HWPROBE_EXT_ZCB`: The Zcb extension part of Zc* standard > + extensions for code size reduction, as ratified in commit 8be3419c1c0 > + ("Zcf doesn't exist on RV64 as it contains no instructions") of > + riscv-code-size-reduction. > + > + * :c:macro:`RISCV_HWPROBE_EXT_ZCD`: The Zcd extension part of Zc* standard > + extensions for code size reduction, as ratified in commit 8be3419c1c0 > + ("Zcf doesn't exist on RV64 as it contains no instructions") of > + riscv-code-size-reduction. > + > + * :c:macro:`RISCV_HWPROBE_EXT_ZCF`: The Zcf extension part of Zc* standard > + extensions for code size reduction, as ratified in commit 8be3419c1c0 > + ("Zcf doesn't exist on RV64 as it contains no instructions") of > + riscv-code-size-reduction. > + > * :c:macro:`RISCV_HWPROBE_KEY_CPUPERF_0`: A bitmask that contains performance > information about the selected set of processors. > > diff --git a/arch/riscv/include/uapi/asm/hwprobe.h b/arch/riscv/include/uapi/asm/hwprobe.h > index 3b16a12204b1..652b2373729f 100644 > --- a/arch/riscv/include/uapi/asm/hwprobe.h > +++ b/arch/riscv/include/uapi/asm/hwprobe.h > @@ -61,6 +61,10 @@ struct riscv_hwprobe { > #define RISCV_HWPROBE_EXT_ZICOND (1ULL << 35) > #define RISCV_HWPROBE_EXT_ZIHINTPAUSE (1ULL << 36) > #define RISCV_HWPROBE_EXT_ZIMOP (1ULL << 37) > +#define RISCV_HWPROBE_EXT_ZCA (1ULL << 38) > +#define RISCV_HWPROBE_EXT_ZCB (1ULL << 39) > +#define RISCV_HWPROBE_EXT_ZCD (1ULL << 40) > +#define RISCV_HWPROBE_EXT_ZCF (1ULL << 41) > #define RISCV_HWPROBE_KEY_CPUPERF_0 5 > #define RISCV_HWPROBE_MISALIGNED_UNKNOWN (0 << 0) > #define RISCV_HWPROBE_MISALIGNED_EMULATED (1 << 0) > diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c > index fc6f4238f0b3..11def345a42d 100644 > --- a/arch/riscv/kernel/sys_hwprobe.c > +++ b/arch/riscv/kernel/sys_hwprobe.c > @@ -113,6 +113,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > EXT_KEY(ZICOND); > EXT_KEY(ZIHINTPAUSE); > EXT_KEY(ZIMOP); > + EXT_KEY(ZCA); > + EXT_KEY(ZCB); > > if (has_vector()) { > EXT_KEY(ZVBB); > @@ -133,6 +135,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair, > EXT_KEY(ZFH); > EXT_KEY(ZFHMIN); > EXT_KEY(ZFA); > + EXT_KEY(ZCD); > + EXT_KEY(ZCF); > } > #undef EXT_KEY > } > -- > 2.43.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
On Fri, May 17, 2024 at 04:52:53PM +0200, Clément Léger wrote: > Add parsing for Zcmop ISA extension which was ratified in commit > b854a709c00 ("Zcmop is ratified/1.0") of the riscv-isa-manual. > > Signed-off-by: Clément Léger <cleger@rivosinc.com> > --- > arch/riscv/include/asm/hwcap.h | 1 + > arch/riscv/kernel/cpufeature.c | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/arch/riscv/include/asm/hwcap.h b/arch/riscv/include/asm/hwcap.h > index a5836fa6b998..aaaf23f204ac 100644 > --- a/arch/riscv/include/asm/hwcap.h > +++ b/arch/riscv/include/asm/hwcap.h > @@ -85,6 +85,7 @@ > #define RISCV_ISA_EXT_ZCB 76 > #define RISCV_ISA_EXT_ZCD 77 > #define RISCV_ISA_EXT_ZCF 78 > +#define RISCV_ISA_EXT_ZCMOP 79 > > #define RISCV_ISA_EXT_XLINUXENVCFG 127 > > diff --git a/arch/riscv/kernel/cpufeature.c b/arch/riscv/kernel/cpufeature.c > index 3bb2ef52a38b..0a40fa1faa04 100644 > --- a/arch/riscv/kernel/cpufeature.c > +++ b/arch/riscv/kernel/cpufeature.c > @@ -290,6 +290,7 @@ const struct riscv_isa_ext_data riscv_isa_ext[] = { > __RISCV_ISA_EXT_DATA_VALIDATE(zcb, RISCV_ISA_EXT_ZCB, riscv_ext_zca_depends), > __RISCV_ISA_EXT_DATA_VALIDATE(zcd, RISCV_ISA_EXT_ZCD, riscv_ext_zcd_validate), > __RISCV_ISA_EXT_DATA_VALIDATE(zcf, RISCV_ISA_EXT_ZCF, riscv_ext_zcf_validate), > + __RISCV_ISA_EXT_DATA_VALIDATE(zcmop, RISCV_ISA_EXT_ZCMOP, riscv_ext_zca_depends), > __RISCV_ISA_EXT_DATA(zba, RISCV_ISA_EXT_ZBA), > __RISCV_ISA_EXT_DATA(zbb, RISCV_ISA_EXT_ZBB), > __RISCV_ISA_EXT_DATA(zbc, RISCV_ISA_EXT_ZBC), > -- > 2.43.0 > > > _______________________________________________ > linux-riscv mailing list > linux-riscv@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-riscv Reviewed-by: Charlie Jenkins <charlie@rivosinc.com>
On Wed, 22 May 2024 00:20:09 PDT (-0700), cleger@rivosinc.com wrote: > > > On 21/05/2024 21:49, Conor Dooley wrote: >> On Fri, May 17, 2024 at 04:52:48PM +0200, Clément Léger wrote: >> >>> +static int riscv_ext_zca_depends(const struct riscv_isa_ext_data *data, >>> + const unsigned long *isa_bitmap) >>> +{ >>> + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) ? 0 : -EPROBE_DEFER; >>> +} >>> +static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data *data, >>> + const unsigned long *isa_bitmap) >>> +{ >>> + return __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && >>> + __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_d) ? 0 : -EPROBE_DEFER; >>> +} >> >> Could you write the logic in these out normally please? I think they'd >> be more understandable (particular this second one) broken down and with >> early return. > > Yes sure. I'll probably make the same thing for zcf_validate as well as > removing the #ifdef and using IS_ENABLED(): > > static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data, > const unsigned long *isa_bitmap) > { > if (IS_ENABLED(CONFIG_64BIT)) > return -EINVAL; > > if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && > __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) > return 0; > > return -EPROBE_DEFER; > } Are you going to send a v6 (sorry if I missed it, I'm trying to untangle all these ISA parsing patch sets). > >> >> Otherwise, >> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> >> >> Cheers, >> Conor.
On 30/05/2024 23:13, Palmer Dabbelt wrote: > On Wed, 22 May 2024 00:20:09 PDT (-0700), cleger@rivosinc.com wrote: >> >> >> On 21/05/2024 21:49, Conor Dooley wrote: >>> On Fri, May 17, 2024 at 04:52:48PM +0200, Clément Léger wrote: >>> >>>> +static int riscv_ext_zca_depends(const struct riscv_isa_ext_data >>>> *data, >>>> + const unsigned long *isa_bitmap) >>>> +{ >>>> + return __riscv_isa_extension_available(isa_bitmap, >>>> RISCV_ISA_EXT_ZCA) ? 0 : -EPROBE_DEFER; >>>> +} >>>> +static int riscv_ext_zcd_validate(const struct riscv_isa_ext_data >>>> *data, >>>> + const unsigned long *isa_bitmap) >>>> +{ >>>> + return __riscv_isa_extension_available(isa_bitmap, >>>> RISCV_ISA_EXT_ZCA) && >>>> + __riscv_isa_extension_available(isa_bitmap, >>>> RISCV_ISA_EXT_d) ? 0 : -EPROBE_DEFER; >>>> +} >>> >>> Could you write the logic in these out normally please? I think they'd >>> be more understandable (particular this second one) broken down and with >>> early return. >> >> Yes sure. I'll probably make the same thing for zcf_validate as well as >> removing the #ifdef and using IS_ENABLED(): >> >> static int riscv_ext_zcf_validate(const struct riscv_isa_ext_data *data, >> const unsigned long *isa_bitmap) >> { >> if (IS_ENABLED(CONFIG_64BIT)) >> return -EINVAL; >> >> if (__riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_ZCA) && >> __riscv_isa_extension_available(isa_bitmap, RISCV_ISA_EXT_f)) >> return 0; >> >> return -EPROBE_DEFER; >> } > > Are you going to send a v6 (sorry if I missed it, I'm trying to untangle > all these ISA parsing patch sets). Yes, I was waiting for more feedback/Rb by it seems like I now have everything I need. I'll send that. Thanks, Clément > >> >>> >>> Otherwise, >>> Reviewed-by: Conor Dooley <conor.dooley@microchip.com> >>> >>> Cheers, >>> Conor.