Message ID | 37d92e2931b646f97f73650c0306adb736bd0efc.1712638210.git.Takahiro.Kuwano@infineon.com |
---|---|
State | New |
Delegated to: | Jagannadha Sutradharudu Teki |
Headers | show |
Series | mtd: spi-nor: Add support for S25FS-S family | expand |
On Tue, Apr 09 2024, tkuw584924@gmail.com wrote: > From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> > > The S25FS064S, S25FS128S, and S25FS256S are the same family of SPI NOR > Flash devices with S25FS512S. Some difference depending on the device > densities are taken care in post SFDP fixup. > > Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> > --- > drivers/mtd/spi/spi-nor-core.c | 24 ++++++++++++++++++------ > drivers/mtd/spi/spi-nor-ids.c | 3 +++ > 2 files changed, 21 insertions(+), 6 deletions(-) > > diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c > index 9620852817..9b81b31e8e 100644 > --- a/drivers/mtd/spi/spi-nor-core.c > +++ b/drivers/mtd/spi/spi-nor-core.c > @@ -3356,12 +3356,24 @@ static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor, > static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor, > struct spi_nor_flash_parameter *params) > { > - /* READ_1_1_2 is not supported */ > - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; > - /* READ_1_1_4 is not supported */ > - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; > - /* PP_1_1_4 is not supported */ > - params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; > + /* > + * The S25FS064S(8MB) supports 1-1-2 and 1-1-4 commands, but params for > + * read ops in SFDP are wrong. The other density parts do not support > + * 1-1-2 and 1-1-4 commands. > + */ > + if (params->size == SZ_8M) { > + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], > + 0, 8, SPINOR_OP_READ_1_1_2, > + SNOR_PROTO_1_1_2); > + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], > + 0, 8, SPINOR_OP_READ_1_1_4, > + SNOR_PROTO_1_1_4); > + } else { > + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; > + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; > + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; > + } > + Reviewed-by: Pratyush Yadav <pratyush@kernel.org> BTW (not directly related to this patch), I looked at the datasheet you provided in the cover letter and it says dual and quad I/O is supported for the 16 MB and 32 MB parts as well. Why do you mask them out here then? > /* Use volatile register to enable quad */ > params->quad_enable = s25fs_s_quad_enable; > } > diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c > index a3dca506a3..9ca1f244f0 100644 > --- a/drivers/mtd/spi/spi-nor-ids.c > +++ b/drivers/mtd/spi/spi-nor-ids.c > @@ -341,6 +341,9 @@ const struct flash_info spi_nor_ids[] = { > { INFO6("s25fl256s0", 0x010219, 0x4d0080, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > { INFO6("s25fl256s1", 0x010219, 0x4d0180, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > + { INFO6("s25fs064s", 0x010217, 0x4d0181, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > + { INFO6("s25fs128s", 0x012018, 0x4d0181, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > + { INFO6("s25fs256s", 0x010219, 0x4d0181, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, > { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },
On 4/9/2024 8:54 PM, Pratyush Yadav wrote: > On Tue, Apr 09 2024, tkuw584924@gmail.com wrote: > >> From: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> >> >> The S25FS064S, S25FS128S, and S25FS256S are the same family of SPI NOR >> Flash devices with S25FS512S. Some difference depending on the device >> densities are taken care in post SFDP fixup. >> >> Signed-off-by: Takahiro Kuwano <Takahiro.Kuwano@infineon.com> >> --- >> drivers/mtd/spi/spi-nor-core.c | 24 ++++++++++++++++++------ >> drivers/mtd/spi/spi-nor-ids.c | 3 +++ >> 2 files changed, 21 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c >> index 9620852817..9b81b31e8e 100644 >> --- a/drivers/mtd/spi/spi-nor-core.c >> +++ b/drivers/mtd/spi/spi-nor-core.c >> @@ -3356,12 +3356,24 @@ static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor, >> static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor, >> struct spi_nor_flash_parameter *params) >> { >> - /* READ_1_1_2 is not supported */ >> - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; >> - /* READ_1_1_4 is not supported */ >> - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; >> - /* PP_1_1_4 is not supported */ >> - params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; >> + /* >> + * The S25FS064S(8MB) supports 1-1-2 and 1-1-4 commands, but params for >> + * read ops in SFDP are wrong. The other density parts do not support >> + * 1-1-2 and 1-1-4 commands. >> + */ >> + if (params->size == SZ_8M) { >> + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], >> + 0, 8, SPINOR_OP_READ_1_1_2, >> + SNOR_PROTO_1_1_2); >> + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], >> + 0, 8, SPINOR_OP_READ_1_1_4, >> + SNOR_PROTO_1_1_4); >> + } else { >> + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; >> + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; >> + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; >> + } >> + > > Reviewed-by: Pratyush Yadav <pratyush@kernel.org> > > BTW (not directly related to this patch), I looked at the datasheet you > provided in the cover letter and it says dual and quad I/O is supported > for the 16 MB and 32 MB parts as well. Why do you mask them out here > then? > In the datasheet, 1-2-2 and 1-4-4 read are named as dual and quad I/O read. 1-1-2 and 1-1-4 read are named as dual and quad output read. Dual and quad I/O read (1-2-2 and 1-4-4) is supported in all S25FS-S parts. Dual and quad output read (1-1-2 and 1-1-4) is only supported in S25FS064S. Thank you for reviewing! Takahiro
diff --git a/drivers/mtd/spi/spi-nor-core.c b/drivers/mtd/spi/spi-nor-core.c index 9620852817..9b81b31e8e 100644 --- a/drivers/mtd/spi/spi-nor-core.c +++ b/drivers/mtd/spi/spi-nor-core.c @@ -3356,12 +3356,24 @@ static int s25fs_s_post_bfpt_fixup(struct spi_nor *nor, static void s25fs_s_post_sfdp_fixup(struct spi_nor *nor, struct spi_nor_flash_parameter *params) { - /* READ_1_1_2 is not supported */ - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; - /* READ_1_1_4 is not supported */ - params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; - /* PP_1_1_4 is not supported */ - params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + /* + * The S25FS064S(8MB) supports 1-1-2 and 1-1-4 commands, but params for + * read ops in SFDP are wrong. The other density parts do not support + * 1-1-2 and 1-1-4 commands. + */ + if (params->size == SZ_8M) { + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_2], + 0, 8, SPINOR_OP_READ_1_1_2, + SNOR_PROTO_1_1_2); + spi_nor_set_read_settings(¶ms->reads[SNOR_CMD_READ_1_1_4], + 0, 8, SPINOR_OP_READ_1_1_4, + SNOR_PROTO_1_1_4); + } else { + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_2; + params->hwcaps.mask &= ~SNOR_HWCAPS_READ_1_1_4; + params->hwcaps.mask &= ~SNOR_HWCAPS_PP_1_1_4; + } + /* Use volatile register to enable quad */ params->quad_enable = s25fs_s_quad_enable; } diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index a3dca506a3..9ca1f244f0 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -341,6 +341,9 @@ const struct flash_info spi_nor_ids[] = { { INFO6("s25fl256s0", 0x010219, 0x4d0080, 256 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO6("s25fl256s1", 0x010219, 0x4d0180, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO6("s25fl512s", 0x010220, 0x4d0080, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fs064s", 0x010217, 0x4d0181, 64 * 1024, 128, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fs128s", 0x012018, 0x4d0181, 64 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, + { INFO6("s25fs256s", 0x010219, 0x4d0181, 64 * 1024, 512, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO6("s25fs512s", 0x010220, 0x4d0081, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_256k", 0x010220, 0x4d00, 256 * 1024, 256, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) }, { INFO("s25fl512s_64k", 0x010220, 0x4d01, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_CLSR) },