Message ID | 20230920154136.33171-1-pbonzini@redhat.com |
---|---|
State | New |
Headers | show |
Series | target/i386: enumerate bit 56 of MSR_IA32_VMX_BASIC | expand |
On 9/20/2023 11:41 PM, Paolo Bonzini wrote: > On parts that enumerate IA32_VMX_BASIC MSR bit as 1, any exception vector > can be delivered with or without an error code if the other consistency > checks are satisfied. > > Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> > --- > target/i386/cpu.c | 1 + > target/i386/cpu.h | 1 + > 2 files changed, 2 insertions(+) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index 6e52c7be1e1..8f334dbbcc2 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -1347,6 +1347,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { > .feat_names = { > [54] = "vmx-ins-outs", > [55] = "vmx-true-ctls", > + [56] = "vmx-any-errcode", > }, > .msr = { > .index = MSR_IA32_VMX_BASIC, > diff --git a/target/i386/cpu.h b/target/i386/cpu.h > index eab610e5cd5..2e09c588f0b 100644 > --- a/target/i386/cpu.h > +++ b/target/i386/cpu.h > @@ -1039,6 +1039,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, > #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) > #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) > #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) > +#define MSR_VMX_BASIC_ANY_ERRCODE (1ULL << 56) > > #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full > #define MSR_VMX_MISC_STORE_LMA (1ULL << 5) Thanks Paolo! I forgot to post refreshed CET QEMU series which includes this bit enabling. Reviewed-by: Yang Weijiang <weijiang.yang@intel.com>
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 6e52c7be1e1..8f334dbbcc2 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -1347,6 +1347,7 @@ FeatureWordInfo feature_word_info[FEATURE_WORDS] = { .feat_names = { [54] = "vmx-ins-outs", [55] = "vmx-true-ctls", + [56] = "vmx-any-errcode", }, .msr = { .index = MSR_IA32_VMX_BASIC, diff --git a/target/i386/cpu.h b/target/i386/cpu.h index eab610e5cd5..2e09c588f0b 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1039,6 +1039,7 @@ uint64_t x86_cpu_get_supported_feature_word(FeatureWord w, #define MSR_VMX_BASIC_DUAL_MONITOR (1ULL << 49) #define MSR_VMX_BASIC_INS_OUTS (1ULL << 54) #define MSR_VMX_BASIC_TRUE_CTLS (1ULL << 55) +#define MSR_VMX_BASIC_ANY_ERRCODE (1ULL << 56) #define MSR_VMX_MISC_PREEMPTION_TIMER_SHIFT_MASK 0x1Full #define MSR_VMX_MISC_STORE_LMA (1ULL << 5)
On parts that enumerate IA32_VMX_BASIC MSR bit as 1, any exception vector can be delivered with or without an error code if the other consistency checks are satisfied. Signed-off-by: Paolo Bonzini <pbonzini@redhat.com> --- target/i386/cpu.c | 1 + target/i386/cpu.h | 1 + 2 files changed, 2 insertions(+)