Message ID | 20220622181723.13033-1-prabhakar.mahadev-lad.rj@bp.renesas.com |
---|---|
Headers | show |
Series | Add CPG wrapper for Renesas RZ/Five SoC | expand |
On Wed, Jun 22, 2022 at 8:17 PM Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> wrote: > Renesas RZ/Five SoC has almost the same clock structure compared to the > Renesas RZ/G2UL SoC, re-use the r9a07g043-cpg.c file to add support for > RZ/Five SoC. > > This patch splits up the clocks and reset arrays for RZ/G2UL and RZ/Five > SoC using #ifdef CONFIG_ARM64 and #ifdef CONFIG_RISCV checks. > > Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue in renesas-clk-for-v5.20. Gr{oetje,eeting}s, Geert -- Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org In personal conversations with technical people, I call myself a hacker. But when I'm talking to journalists I just say "programmer" or something like that. -- Linus Torvalds