Message ID | 20210910184147.336618-1-paul.kocialkowski@bootlin.com |
---|---|
Headers | show |
Series | Allwinner A31/A83T MIPI CSI-2 Support and A31 ISP Support | expand |
On 9/10/21 1:41 PM, Paul Kocialkowski wrote: > MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge > controller. The controller uses a separate D-PHY, which is the same > that is otherwise used for MIPI DSI, but used in Rx mode. > > On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does > not have access to any parallel interface pins. > > Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to > support the MIPI CSI-2 interface. > > Note that a fwnode graph link is created between CSI0 and MIPI CSI-2 > even when no sensor is connected. This will result in a probe failure > for the controller as long as no sensor is connected but this is fine > since no other interface is available. > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > --- > arch/arm/boot/dts/sun8i-v3s.dtsi | 72 ++++++++++++++++++++++++++++++++ > 1 file changed, 72 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi > index a77b63362a1d..ec7fa6459547 100644 > --- a/arch/arm/boot/dts/sun8i-v3s.dtsi > +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi > @@ -612,6 +612,34 @@ spi0: spi@1c68000 { > #size-cells = <0>; > }; > > + csi0: camera@1cb0000 { > + compatible = "allwinner,sun8i-v3s-csi"; > + reg = <0x01cb0000 0x1000>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI1_SCLK>, > + <&ccu CLK_DRAM_CSI>; > + clock-names = "bus", "mod", "ram"; > + resets = <&ccu RST_BUS_CSI>; > + status = "disabled"; > + > + assigned-clocks = <&ccu CLK_CSI1_SCLK>; > + assigned-clock-parents = <&ccu CLK_PLL_ISP>; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + port@1 { > + reg = <1>; > + > + csi0_in_mipi_csi2: endpoint { > + remote-endpoint = <&mipi_csi2_out_csi0>; > + }; > + }; > + }; > + }; > + > csi1: camera@1cb4000 { > compatible = "allwinner,sun8i-v3s-csi"; > reg = <0x01cb4000 0x3000>; All of the new nodes should be added above this one, to maintain unit address order. Regards, Samuel > @@ -637,5 +665,49 @@ gic: interrupt-controller@1c81000 { > #interrupt-cells = <3>; > interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > }; > + > + mipi_csi2: csi@1cb1000 { > + compatible = "allwinner,sun8i-v3s-mipi-csi2", > + "allwinner,sun6i-a31-mipi-csi2"; > + reg = <0x01cb1000 0x1000>; > + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI1_SCLK>; > + clock-names = "bus", "mod"; > + resets = <&ccu RST_BUS_CSI>; > + status = "disabled"; > + > + phys = <&dphy>; > + phy-names = "dphy"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + mipi_csi2_in: port@0 { > + reg = <0>; > + }; > + > + mipi_csi2_out: port@1 { > + reg = <1>; > + > + mipi_csi2_out_csi0: endpoint { > + remote-endpoint = <&csi0_in_mipi_csi2>; > + }; > + }; > + }; > + }; > + > + dphy: d-phy@1cb2000 { > + compatible = "allwinner,sun6i-a31-mipi-dphy"; > + reg = <0x01cb2000 0x1000>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_MIPI_CSI>; > + clock-names = "bus", "mod"; > + resets = <&ccu RST_BUS_CSI>; > + allwinner,direction = "rx"; > + status = "disabled"; > + #phy-cells = <0>; > + }; > }; > }; >
On 9/10/21 1:41 PM, Paul Kocialkowski wrote: > The A31 ISP sits on the mbus and requires the usual bus address > adaptation. Add its compatibles to the list. My understanding is that this driver only exists to work around old DT bindings where the interconnects/interconnect-names = "dma-mem" properties are not required (and so they are historically missing from the device trees). For new bindings, it would be better to use those properties and not add to this list. Regards, Samuel > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > --- > drivers/soc/sunxi/sunxi_mbus.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/soc/sunxi/sunxi_mbus.c b/drivers/soc/sunxi/sunxi_mbus.c > index d90e4a264b6f..7f0079ea30b1 100644 > --- a/drivers/soc/sunxi/sunxi_mbus.c > +++ b/drivers/soc/sunxi/sunxi_mbus.c > @@ -37,6 +37,7 @@ static const char * const sunxi_mbus_devices[] = { > "allwinner,sun5i-a13-video-engine", > "allwinner,sun6i-a31-csi", > "allwinner,sun6i-a31-display-backend", > + "allwinner,sun6i-a31-isp", > "allwinner,sun7i-a20-csi0", > "allwinner,sun7i-a20-display-backend", > "allwinner,sun7i-a20-display-frontend", > @@ -50,6 +51,7 @@ static const char * const sunxi_mbus_devices[] = { > "allwinner,sun8i-h3-csi", > "allwinner,sun8i-h3-video-engine", > "allwinner,sun8i-v3s-csi", > + "allwinner,sun8i-v3s-isp", > "allwinner,sun9i-a80-display-backend", > "allwinner,sun50i-a64-csi", > "allwinner,sun50i-a64-video-engine", >
Hi, On Sat, Sep 11, 2021 at 2:42 AM Paul Kocialkowski <paul.kocialkowski@bootlin.com> wrote: > > MIPI CSI-2 is supported on the A83T with a dedicated controller that > covers both the protocol and D-PHY. It can be connected to the CSI > interface as a V4L2 subdev through the fwnode graph. > > This is not done by default since connecting the bridge without a > subdev attached to it will cause a failure on the CSI driver. > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> I believe you tagged the wrong patch to not be merged? AFAICT it should be the next patch that hooks up OV8865, not this one. > --- > arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++++++++++++++++++++++++++ > 1 file changed, 26 insertions(+) > > diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi > index ac97eac91349..1fa51f7ef063 100644 > --- a/arch/arm/boot/dts/sun8i-a83t.dtsi > +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi > @@ -1064,6 +1064,32 @@ csi: camera@1cb0000 { > status = "disabled"; > }; > > + mipi_csi2: csi@1cb1000 { > + compatible = "allwinner,sun8i-a83t-mipi-csi2"; > + reg = <0x01cb1000 0x1000>; > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&ccu CLK_BUS_CSI>, > + <&ccu CLK_CSI_SCLK>, > + <&ccu CLK_MIPI_CSI>, > + <&ccu CLK_CSI_MISC>; > + clock-names = "bus", "mod", "mipi", "misc"; > + resets = <&ccu RST_BUS_CSI>; > + status = "disabled"; > + > + ports { > + #address-cells = <1>; > + #size-cells = <0>; > + > + mipi_csi2_in: port@0 { > + reg = <0>; > + }; > + > + mipi_csi2_out: port@1 { > + reg = <1>; > + }; > + }; > + }; > + > hdmi: hdmi@1ee0000 { > compatible = "allwinner,sun8i-a83t-dw-hdmi"; > reg = <0x01ee0000 0x10000>; > -- > 2.32.0 > >
Hi Samuel, On Fri 10 Sep 21, 21:32, Samuel Holland wrote: > On 9/10/21 1:41 PM, Paul Kocialkowski wrote: > > MIPI CSI-2 is supported on the V3s with an A31-based MIPI CSI-2 bridge > > controller. The controller uses a separate D-PHY, which is the same > > that is otherwise used for MIPI DSI, but used in Rx mode. > > > > On the V3s, the CSI0 controller is dedicated to MIPI CSI-2 as it does > > not have access to any parallel interface pins. > > > > Add all the necessary nodes (CSI0, MIPI CSI-2 bridge and D-PHY) to > > support the MIPI CSI-2 interface. > > > > Note that a fwnode graph link is created between CSI0 and MIPI CSI-2 > > even when no sensor is connected. This will result in a probe failure > > for the controller as long as no sensor is connected but this is fine > > since no other interface is available. > > > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > > --- > > arch/arm/boot/dts/sun8i-v3s.dtsi | 72 ++++++++++++++++++++++++++++++++ > > 1 file changed, 72 insertions(+) > > > > diff --git a/arch/arm/boot/dts/sun8i-v3s.dtsi b/arch/arm/boot/dts/sun8i-v3s.dtsi > > index a77b63362a1d..ec7fa6459547 100644 > > --- a/arch/arm/boot/dts/sun8i-v3s.dtsi > > +++ b/arch/arm/boot/dts/sun8i-v3s.dtsi > > @@ -612,6 +612,34 @@ spi0: spi@1c68000 { > > #size-cells = <0>; > > }; > > > > + csi0: camera@1cb0000 { > > + compatible = "allwinner,sun8i-v3s-csi"; > > + reg = <0x01cb0000 0x1000>; > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_CSI1_SCLK>, > > + <&ccu CLK_DRAM_CSI>; > > + clock-names = "bus", "mod", "ram"; > > + resets = <&ccu RST_BUS_CSI>; > > + status = "disabled"; > > + > > + assigned-clocks = <&ccu CLK_CSI1_SCLK>; > > + assigned-clock-parents = <&ccu CLK_PLL_ISP>; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + port@1 { > > + reg = <1>; > > + > > + csi0_in_mipi_csi2: endpoint { > > + remote-endpoint = <&mipi_csi2_out_csi0>; > > + }; > > + }; > > + }; > > + }; > > + > > csi1: camera@1cb4000 { > > compatible = "allwinner,sun8i-v3s-csi"; > > reg = <0x01cb4000 0x3000>; > > All of the new nodes should be added above this one, to maintain unit > address order. Good catch, this was an overlook on my side. Thanks, Paul > Regards, > Samuel > > > @@ -637,5 +665,49 @@ gic: interrupt-controller@1c81000 { > > #interrupt-cells = <3>; > > interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; > > }; > > + > > + mipi_csi2: csi@1cb1000 { > > + compatible = "allwinner,sun8i-v3s-mipi-csi2", > > + "allwinner,sun6i-a31-mipi-csi2"; > > + reg = <0x01cb1000 0x1000>; > > + interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_CSI1_SCLK>; > > + clock-names = "bus", "mod"; > > + resets = <&ccu RST_BUS_CSI>; > > + status = "disabled"; > > + > > + phys = <&dphy>; > > + phy-names = "dphy"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + mipi_csi2_in: port@0 { > > + reg = <0>; > > + }; > > + > > + mipi_csi2_out: port@1 { > > + reg = <1>; > > + > > + mipi_csi2_out_csi0: endpoint { > > + remote-endpoint = <&csi0_in_mipi_csi2>; > > + }; > > + }; > > + }; > > + }; > > + > > + dphy: d-phy@1cb2000 { > > + compatible = "allwinner,sun6i-a31-mipi-dphy"; > > + reg = <0x01cb2000 0x1000>; > > + clocks = <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_MIPI_CSI>; > > + clock-names = "bus", "mod"; > > + resets = <&ccu RST_BUS_CSI>; > > + allwinner,direction = "rx"; > > + status = "disabled"; > > + #phy-cells = <0>; > > + }; > > }; > > }; > > >
Hi Samuel, On Fri 10 Sep 21, 21:36, Samuel Holland wrote: > On 9/10/21 1:41 PM, Paul Kocialkowski wrote: > > The A31 ISP sits on the mbus and requires the usual bus address > > adaptation. Add its compatibles to the list. > > My understanding is that this driver only exists to work around old DT > bindings where the interconnects/interconnect-names = "dma-mem" > properties are not required (and so they are historically missing from > the device trees). > > For new bindings, it would be better to use those properties and not add > to this list. Oh okay, I didn't really look into it and just did the same thing that was done for the CSI controller. Thanks for the heads up! Paul > Regards, > Samuel > > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > > --- > > drivers/soc/sunxi/sunxi_mbus.c | 2 ++ > > 1 file changed, 2 insertions(+) > > > > diff --git a/drivers/soc/sunxi/sunxi_mbus.c b/drivers/soc/sunxi/sunxi_mbus.c > > index d90e4a264b6f..7f0079ea30b1 100644 > > --- a/drivers/soc/sunxi/sunxi_mbus.c > > +++ b/drivers/soc/sunxi/sunxi_mbus.c > > @@ -37,6 +37,7 @@ static const char * const sunxi_mbus_devices[] = { > > "allwinner,sun5i-a13-video-engine", > > "allwinner,sun6i-a31-csi", > > "allwinner,sun6i-a31-display-backend", > > + "allwinner,sun6i-a31-isp", > > "allwinner,sun7i-a20-csi0", > > "allwinner,sun7i-a20-display-backend", > > "allwinner,sun7i-a20-display-frontend", > > @@ -50,6 +51,7 @@ static const char * const sunxi_mbus_devices[] = { > > "allwinner,sun8i-h3-csi", > > "allwinner,sun8i-h3-video-engine", > > "allwinner,sun8i-v3s-csi", > > + "allwinner,sun8i-v3s-isp", > > "allwinner,sun9i-a80-display-backend", > > "allwinner,sun50i-a64-csi", > > "allwinner,sun50i-a64-video-engine", > > >
Hi Chen-Yu, On Sat 11 Sep 21, 10:53, Chen-Yu Tsai wrote: > Hi, > > On Sat, Sep 11, 2021 at 2:42 AM Paul Kocialkowski > <paul.kocialkowski@bootlin.com> wrote: > > > > MIPI CSI-2 is supported on the A83T with a dedicated controller that > > covers both the protocol and D-PHY. It can be connected to the CSI > > interface as a V4L2 subdev through the fwnode graph. > > > > This is not done by default since connecting the bridge without a > > subdev attached to it will cause a failure on the CSI driver. > > > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > > I believe you tagged the wrong patch to not be merged? AFAICT it > should be the next patch that hooks up OV8865, not this one. Yes you are definitely right, this patch is good for merge and the next one is not. Thanks, Paul > > --- > > arch/arm/boot/dts/sun8i-a83t.dtsi | 26 ++++++++++++++++++++++++++ > > 1 file changed, 26 insertions(+) > > > > diff --git a/arch/arm/boot/dts/sun8i-a83t.dtsi b/arch/arm/boot/dts/sun8i-a83t.dtsi > > index ac97eac91349..1fa51f7ef063 100644 > > --- a/arch/arm/boot/dts/sun8i-a83t.dtsi > > +++ b/arch/arm/boot/dts/sun8i-a83t.dtsi > > @@ -1064,6 +1064,32 @@ csi: camera@1cb0000 { > > status = "disabled"; > > }; > > > > + mipi_csi2: csi@1cb1000 { > > + compatible = "allwinner,sun8i-a83t-mipi-csi2"; > > + reg = <0x01cb1000 0x1000>; > > + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; > > + clocks = <&ccu CLK_BUS_CSI>, > > + <&ccu CLK_CSI_SCLK>, > > + <&ccu CLK_MIPI_CSI>, > > + <&ccu CLK_CSI_MISC>; > > + clock-names = "bus", "mod", "mipi", "misc"; > > + resets = <&ccu RST_BUS_CSI>; > > + status = "disabled"; > > + > > + ports { > > + #address-cells = <1>; > > + #size-cells = <0>; > > + > > + mipi_csi2_in: port@0 { > > + reg = <0>; > > + }; > > + > > + mipi_csi2_out: port@1 { > > + reg = <1>; > > + }; > > + }; > > + }; > > + > > hdmi: hdmi@1ee0000 { > > compatible = "allwinner,sun8i-a83t-dw-hdmi"; > > reg = <0x01ee0000 0x10000>; > > -- > > 2.32.0 > > > >
On Fri, Sep 10, 2021 at 08:41:40PM +0200, Paul Kocialkowski wrote: > As described in the commit adding support for the new sun6i-csi driver, > a complete rewrite was necessary to support the Allwinner A31 ISP as > well as fix a number of issues with the current implementation. > > Farewell and thanks for all the pixels! > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> For completeness, this is what the other commit log mentions: > While adapting the sun6i-csi driver for MIPI CSI-2 support was > possible, it became clear that adding support for the ISP required > very heavy changes to the driver which were quite hard to break down > into a series of subsequent changes. > The first major difficulty comes from the lack of v4l2 subdev that > acts a bridge, separate from the video node representing the DMA > engine. To support the ISP, only parts of the hardware must be > configured (excluding aspects related to the DMA output), which made > the separation a hard requirement. > Another significant difficulty was the specific dance that is required > to have both the ISP and CSI device be part of the same media device. > Because the ISP and CSI are two different hardware blocks, they have > two distinct drivers that will each try to register their own v4l2 > and media devices, resulting in two distinct pipelines. When the ISP > is in use, we actually want the CSI driver to register with the ISP's > v4l2 and media devices while keeping the ability to register its own > when the ISP is not in use. This is done by: > 1. Having the CSI driver check whether the ISP is available, using > sun6i_csi_isp_detect(); > 2. If not, it can register when its own async subdevs are ready, using > sun6i_csi_v4l2_complete(); > 3. If so, it will register its bridge as an async subdev which will > be picked-up by the ISP driver (from the fwnode graph link); > 4. When the subdev becomes bound to the ISP's v4l2 device, we can > then access that device (and the associated media device) to > complete registration of the capture video node, using > sun6i_csi_isp_complete(); > Besides the logic rework, other issues were identified and resolved: > - The sync mechanism for buffer flipping was based on the frame done > interrupt, which is too late (next frame is already being processed). > This lead to requiring 3 buffers to start and writing two addresses > when starting. Using vsync as a sync point seems to be the correct > approach and allows using only two buffers without tearing; > - Using devm_regmap_init_mmio_clk was incorrect since the reset also > comes into play; > - Some register definitions were inverted compared to their actual > effect (which was inherited from the Allwinner documentation and > code): comments were added where relevant; > - The deprecated v4l2_async_notifier_parse_fwnode_endpoints() helper > is no longer used by the driver; With that being said, NAK. Having heavy changes to a driver is completely fine, and is kind of expected really with such a big change. Breaking all possibility of bisection and throwing away years of stabilization and maintenance isn't. And all those small bug fixes you mention at the end are just that: small bug fixes that can be done on the current driver just fine too. Maxime
On Fri, Sep 10, 2021 at 08:41:45PM +0200, Paul Kocialkowski wrote: > Some Allwinner platforms come with an Image Signal Processor, which > supports various features in order to enhance and transform data > received by image sensors into good-looking pictures. In most cases, > the data is raw bayer, which gets internally converted to RGB and > finally YUV, which is what the hardware produces. > > This driver supports ISPs that are similar to the A31 ISP, which was > the first standalone ISP found in Allwinner platforms. Simpler ISP > blocks were found in the A10 and A20, where they are tied to a CSI > controller. Newer generations of Allwinner SoCs (starting with the > H6, H616, etc) come with a new camera subsystem and revised ISP. > Even though these previous and next-generation ISPs are somewhat > similar to the A31 ISP, they have enough significant differences to > be out of the scope of this driver. > > While the ISP supports many features, including 3A and many > enhancement blocks, this implementation is limited to the following: > - V3s (V3/S3) platform support; > - Bayer media bus formats as input; > - Semi-planar YUV (NV12/NV21) as output; > - Debayering with per-component gain and offset configuration; > - 2D noise filtering with configurable coefficients. > > Since many features are missing from the associated uAPI, the driver > is aimed to integrate staging until all features are properly > described. We can add new features/interfaces to a !staging driver. Why do you think staging is required? > On the technical side, it uses the v4l2 and media controller APIs, > with a video node for capture, a processor subdev and a video node > for parameters submission. A specific uAPI structure and associated > v4l2 meta format are used to configure parameters of the supported > modules. This meta format needs to be documented Maxime
On Mon, Sep 13, 2021 at 09:45:22AM +0200, Paul Kocialkowski wrote: > Hi Samuel, > > On Fri 10 Sep 21, 21:36, Samuel Holland wrote: > > On 9/10/21 1:41 PM, Paul Kocialkowski wrote: > > > The A31 ISP sits on the mbus and requires the usual bus address > > > adaptation. Add its compatibles to the list. > > > > My understanding is that this driver only exists to work around old DT > > bindings where the interconnects/interconnect-names = "dma-mem" > > properties are not required (and so they are historically missing from > > the device trees). > > > > For new bindings, it would be better to use those properties and not add > > to this list. > > Oh okay, I didn't really look into it and just did the same thing that was > done for the CSI controller. Thanks for the heads up! This code was done to maintain backward compatibility. New DT should indeed use the interconnects property. Maxime
Hi, On Mon 13 Sep 21, 10:31, Maxime Ripard wrote: > On Fri, Sep 10, 2021 at 08:41:45PM +0200, Paul Kocialkowski wrote: > > Some Allwinner platforms come with an Image Signal Processor, which > > supports various features in order to enhance and transform data > > received by image sensors into good-looking pictures. In most cases, > > the data is raw bayer, which gets internally converted to RGB and > > finally YUV, which is what the hardware produces. > > > > This driver supports ISPs that are similar to the A31 ISP, which was > > the first standalone ISP found in Allwinner platforms. Simpler ISP > > blocks were found in the A10 and A20, where they are tied to a CSI > > controller. Newer generations of Allwinner SoCs (starting with the > > H6, H616, etc) come with a new camera subsystem and revised ISP. > > Even though these previous and next-generation ISPs are somewhat > > similar to the A31 ISP, they have enough significant differences to > > be out of the scope of this driver. > > > > While the ISP supports many features, including 3A and many > > enhancement blocks, this implementation is limited to the following: > > - V3s (V3/S3) platform support; > > - Bayer media bus formats as input; > > - Semi-planar YUV (NV12/NV21) as output; > > - Debayering with per-component gain and offset configuration; > > - 2D noise filtering with configurable coefficients. > > > > Since many features are missing from the associated uAPI, the driver > > is aimed to integrate staging until all features are properly > > described. > > We can add new features/interfaces to a !staging driver. Why do you > think staging is required? This is true for the driver but not so much for the uAPI, so it seems that the uAPI must be added to staging in some way. Then I'm not sure it makes sense to have a !staging driver that depends on a staging uAPI. Besides that, I added it to staging because that's the process that was followed by rkisp1, which is a very similar case. > > On the technical side, it uses the v4l2 and media controller APIs, > > with a video node for capture, a processor subdev and a video node > > for parameters submission. A specific uAPI structure and associated > > v4l2 meta format are used to configure parameters of the supported > > modules. > > This meta format needs to be documented You're right, there should probably be a pixfmt-meta-sun6i-isp.rst documentation file. I guess it should live along in the staging driver directory for now and be destaged later. Cheers, Paul
Hi, On Mon 13 Sep 21, 10:17, Maxime Ripard wrote: > On Fri, Sep 10, 2021 at 08:41:40PM +0200, Paul Kocialkowski wrote: > > As described in the commit adding support for the new sun6i-csi driver, > > a complete rewrite was necessary to support the Allwinner A31 ISP as > > well as fix a number of issues with the current implementation. > > > > Farewell and thanks for all the pixels! > > > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > > For completeness, this is what the other commit log mentions: > > > While adapting the sun6i-csi driver for MIPI CSI-2 support was > > possible, it became clear that adding support for the ISP required > > very heavy changes to the driver which were quite hard to break down > > into a series of subsequent changes. > > > The first major difficulty comes from the lack of v4l2 subdev that > > acts a bridge, separate from the video node representing the DMA > > engine. To support the ISP, only parts of the hardware must be > > configured (excluding aspects related to the DMA output), which made > > the separation a hard requirement. > > > Another significant difficulty was the specific dance that is required > > to have both the ISP and CSI device be part of the same media device. > > Because the ISP and CSI are two different hardware blocks, they have > > two distinct drivers that will each try to register their own v4l2 > > and media devices, resulting in two distinct pipelines. When the ISP > > is in use, we actually want the CSI driver to register with the ISP's > > v4l2 and media devices while keeping the ability to register its own > > when the ISP is not in use. This is done by: > > 1. Having the CSI driver check whether the ISP is available, using > > sun6i_csi_isp_detect(); > > 2. If not, it can register when its own async subdevs are ready, using > > sun6i_csi_v4l2_complete(); > > 3. If so, it will register its bridge as an async subdev which will > > be picked-up by the ISP driver (from the fwnode graph link); > > 4. When the subdev becomes bound to the ISP's v4l2 device, we can > > then access that device (and the associated media device) to > > complete registration of the capture video node, using > > sun6i_csi_isp_complete(); > > Besides the logic rework, other issues were identified and resolved: > > - The sync mechanism for buffer flipping was based on the frame done > > interrupt, which is too late (next frame is already being processed). > > This lead to requiring 3 buffers to start and writing two addresses > > when starting. Using vsync as a sync point seems to be the correct > > approach and allows using only two buffers without tearing; > > - Using devm_regmap_init_mmio_clk was incorrect since the reset also > > comes into play; > > - Some register definitions were inverted compared to their actual > > effect (which was inherited from the Allwinner documentation and > > code): comments were added where relevant; > > - The deprecated v4l2_async_notifier_parse_fwnode_endpoints() helper > > is no longer used by the driver; > > With that being said, NAK. > > Having heavy changes to a driver is completely fine, and is kind of > expected really with such a big change. Breaking all possibility of > bisection and throwing away years of stabilization and maintenance > isn't. > > And all those small bug fixes you mention at the end are just that: > small bug fixes that can be done on the current driver just fine too. I understand that this looks like we're trashing all the work that was done previously by removing the current driver and adding the new one but the logic for deciding what to write into registers was carefully preserved from the original driver to make sure that the works of stabilization and maintenance are not lost. However I would understand that my good promise on this is not enough, so perhaps I could provide a combinatory verification that the same set of mbus/pixel formats end up with the same thing being written into registers. In addition I understand that it will be necessary to split the changes up into small commits to clarify the transition path between the two drivers. So I will do my best to split things up. Does that seem like an agreeable plan or do you see other things that would be blockers? My initial thought was that it would be much easier to review the driver as a rewrite, but I'm not too surprised I was wrong. To be honest it was nearly impossible to actually have the initial development happen as sequential steps and I preferred to allocate my time on other tasks than splitting the changes into these sequential steps. Cheers, Paul
Hi Paul, On Tue, Sep 14, 2021 at 09:50:41AM +0200, Paul Kocialkowski wrote: > On Mon 13 Sep 21, 10:31, Maxime Ripard wrote: > > On Fri, Sep 10, 2021 at 08:41:45PM +0200, Paul Kocialkowski wrote: > > > Some Allwinner platforms come with an Image Signal Processor, which > > > supports various features in order to enhance and transform data > > > received by image sensors into good-looking pictures. In most cases, > > > the data is raw bayer, which gets internally converted to RGB and > > > finally YUV, which is what the hardware produces. > > > > > > This driver supports ISPs that are similar to the A31 ISP, which was > > > the first standalone ISP found in Allwinner platforms. Simpler ISP > > > blocks were found in the A10 and A20, where they are tied to a CSI > > > controller. Newer generations of Allwinner SoCs (starting with the > > > H6, H616, etc) come with a new camera subsystem and revised ISP. > > > Even though these previous and next-generation ISPs are somewhat > > > similar to the A31 ISP, they have enough significant differences to > > > be out of the scope of this driver. > > > > > > While the ISP supports many features, including 3A and many > > > enhancement blocks, this implementation is limited to the following: > > > - V3s (V3/S3) platform support; > > > - Bayer media bus formats as input; > > > - Semi-planar YUV (NV12/NV21) as output; > > > - Debayering with per-component gain and offset configuration; > > > - 2D noise filtering with configurable coefficients. > > > > > > Since many features are missing from the associated uAPI, the driver > > > is aimed to integrate staging until all features are properly > > > described. > > > > We can add new features/interfaces to a !staging driver. Why do you > > think staging is required? > > This is true for the driver but not so much for the uAPI, so it seems that > the uAPI must be added to staging in some way. Then I'm not sure it makes sense > to have a !staging driver that depends on a staging uAPI. > > Besides that, I added it to staging because that's the process that was > followed by rkisp1, which is a very similar case. Maxime is right in the sense that uAPI can always be extended, but it has to be done in a backward-compatible manner, and staging is sometimes considered as not being covered by the ABI stability requirements of the kernel. Not everybody agrees on this, but there are clear cases where userspace really can't expect staging ABIs to be stable (for instance when the driver doesn't even compile). I think there's value in having the driver in staging to facilitate development until we consider the ABI stable, but I'm not entirely sure if there should be another step taken to mark this ABI is not being ready yet. > > > On the technical side, it uses the v4l2 and media controller APIs, > > > with a video node for capture, a processor subdev and a video node > > > for parameters submission. A specific uAPI structure and associated > > > v4l2 meta format are used to configure parameters of the supported > > > modules. > > > > This meta format needs to be documented > > You're right, there should probably be a pixfmt-meta-sun6i-isp.rst > documentation file. I guess it should live along in the staging driver > directory for now and be destaged later. Can documentation in staging be compiled ? If not I think it can go to Documentation/
On Tue, Sep 14, 2021 at 02:11:18PM +0300, Laurent Pinchart wrote: > Hi Paul, > > On Tue, Sep 14, 2021 at 09:50:41AM +0200, Paul Kocialkowski wrote: > > On Mon 13 Sep 21, 10:31, Maxime Ripard wrote: > > > On Fri, Sep 10, 2021 at 08:41:45PM +0200, Paul Kocialkowski wrote: > > > > Some Allwinner platforms come with an Image Signal Processor, which > > > > supports various features in order to enhance and transform data > > > > received by image sensors into good-looking pictures. In most cases, > > > > the data is raw bayer, which gets internally converted to RGB and > > > > finally YUV, which is what the hardware produces. > > > > > > > > This driver supports ISPs that are similar to the A31 ISP, which was > > > > the first standalone ISP found in Allwinner platforms. Simpler ISP > > > > blocks were found in the A10 and A20, where they are tied to a CSI > > > > controller. Newer generations of Allwinner SoCs (starting with the > > > > H6, H616, etc) come with a new camera subsystem and revised ISP. > > > > Even though these previous and next-generation ISPs are somewhat > > > > similar to the A31 ISP, they have enough significant differences to > > > > be out of the scope of this driver. > > > > > > > > While the ISP supports many features, including 3A and many > > > > enhancement blocks, this implementation is limited to the following: > > > > - V3s (V3/S3) platform support; > > > > - Bayer media bus formats as input; > > > > - Semi-planar YUV (NV12/NV21) as output; > > > > - Debayering with per-component gain and offset configuration; > > > > - 2D noise filtering with configurable coefficients. > > > > > > > > Since many features are missing from the associated uAPI, the driver > > > > is aimed to integrate staging until all features are properly > > > > described. > > > > > > We can add new features/interfaces to a !staging driver. Why do you > > > think staging is required? > > > > This is true for the driver but not so much for the uAPI, so it seems that > > the uAPI must be added to staging in some way. Then I'm not sure it makes sense > > to have a !staging driver that depends on a staging uAPI. > > > > Besides that, I added it to staging because that's the process that was > > followed by rkisp1, which is a very similar case. > > Maxime is right in the sense that uAPI can always be extended, but it > has to be done in a backward-compatible manner, and staging is sometimes > considered as not being covered by the ABI stability requirements of the > kernel. Not everybody agrees on this, but there are clear cases where > userspace really can't expect staging ABIs to be stable (for instance > when the driver doesn't even compile). > > I think there's value in having the driver in staging to facilitate > development until we consider the ABI stable, but I'm not entirely sure > if there should be another step taken to mark this ABI is not being > ready yet. The rule seems to be about whether or not the user-space gets broken in the process: https://lore.kernel.org/lkml/CAHk-=wiVi7mSrsMP=fLXQrXK_UimybW=ziLOwSzFTtoXUacWVQ@mail.gmail.com/ Something that wouldn't compile cannot generate a regression, since it never worked in the first place. Changing the semantic of an ioctl does. Maxime
Hi Paul, Maxime, On Tue, Sep 14, 2021 at 10:04:25AM +0200, Paul Kocialkowski wrote: > Hi, > > On Mon 13 Sep 21, 10:17, Maxime Ripard wrote: > > On Fri, Sep 10, 2021 at 08:41:40PM +0200, Paul Kocialkowski wrote: > > > As described in the commit adding support for the new sun6i-csi driver, > > > a complete rewrite was necessary to support the Allwinner A31 ISP as > > > well as fix a number of issues with the current implementation. > > > > > > Farewell and thanks for all the pixels! > > > > > > Signed-off-by: Paul Kocialkowski <paul.kocialkowski@bootlin.com> > > > > For completeness, this is what the other commit log mentions: > > > > > While adapting the sun6i-csi driver for MIPI CSI-2 support was > > > possible, it became clear that adding support for the ISP required > > > very heavy changes to the driver which were quite hard to break down > > > into a series of subsequent changes. > > > > > The first major difficulty comes from the lack of v4l2 subdev that > > > acts a bridge, separate from the video node representing the DMA > > > engine. To support the ISP, only parts of the hardware must be > > > configured (excluding aspects related to the DMA output), which made > > > the separation a hard requirement. > > > > > Another significant difficulty was the specific dance that is required > > > to have both the ISP and CSI device be part of the same media device. > > > Because the ISP and CSI are two different hardware blocks, they have > > > two distinct drivers that will each try to register their own v4l2 > > > and media devices, resulting in two distinct pipelines. When the ISP > > > is in use, we actually want the CSI driver to register with the ISP's > > > v4l2 and media devices while keeping the ability to register its own > > > when the ISP is not in use. This is done by: > > > 1. Having the CSI driver check whether the ISP is available, using > > > sun6i_csi_isp_detect(); > > > 2. If not, it can register when its own async subdevs are ready, using > > > sun6i_csi_v4l2_complete(); > > > 3. If so, it will register its bridge as an async subdev which will > > > be picked-up by the ISP driver (from the fwnode graph link); > > > 4. When the subdev becomes bound to the ISP's v4l2 device, we can > > > then access that device (and the associated media device) to > > > complete registration of the capture video node, using > > > sun6i_csi_isp_complete(); > > > Besides the logic rework, other issues were identified and resolved: > > > - The sync mechanism for buffer flipping was based on the frame done > > > interrupt, which is too late (next frame is already being processed). > > > This lead to requiring 3 buffers to start and writing two addresses > > > when starting. Using vsync as a sync point seems to be the correct > > > approach and allows using only two buffers without tearing; > > > - Using devm_regmap_init_mmio_clk was incorrect since the reset also > > > comes into play; > > > - Some register definitions were inverted compared to their actual > > > effect (which was inherited from the Allwinner documentation and > > > code): comments were added where relevant; > > > - The deprecated v4l2_async_notifier_parse_fwnode_endpoints() helper > > > is no longer used by the driver; > > > > With that being said, NAK. > > > > Having heavy changes to a driver is completely fine, and is kind of > > expected really with such a big change. Breaking all possibility of > > bisection and throwing away years of stabilization and maintenance > > isn't. > > > > And all those small bug fixes you mention at the end are just that: > > small bug fixes that can be done on the current driver just fine too. > > I understand that this looks like we're trashing all the work that was > done previously by removing the current driver and adding the new one > but the logic for deciding what to write into registers was carefully > preserved from the original driver to make sure that the works of > stabilization and maintenance are not lost. > > However I would understand that my good promise on this is not enough, > so perhaps I could provide a combinatory verification that the same set > of mbus/pixel formats end up with the same thing being written into > registers. > > In addition I understand that it will be necessary to split the changes > up into small commits to clarify the transition path between the two > drivers. So I will do my best to split things up. > > Does that seem like an agreeable plan or do you see other things that > would be blockers? Please do refactor the patches into reviewable chunks that make sense on their own. I'd see the result being the same driver but with additional patches fixing bugs, doing some or more refactoring and adding new functionality. Please use -C100 -M100 if there's a need to rename files, and preferrably do so in separate patches. See e.g. patches to the smiapp driver that turned it into a CCS driver: git log 2db8166f739e75c1269d7e8afe8da68e70098810..b24cc2a18c50e4e315abc76a86b26b4c49652f79~ -- drivers/media/i2c/smiapp git log drivers/media/i2c/ccs Usually bugfixes are best put first. > > My initial thought was that it would be much easier to review the driver as a > rewrite, but I'm not too surprised I was wrong. To be honest it was nearly > impossible to actually have the initial development happen as sequential steps > and I preferred to allocate my time on other tasks than splitting the changes > into these sequential steps. This isn't really unusual when you're changing an existing driver: sometimes you have to implement what you want to achieve in whole, and only then figure out how to split it into something that can be reviewed. Often the end result will look different than what you arrived with on the first time.