| Message ID | 20210721225329.3035779-1-bjorn.andersson@linaro.org |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | clk: qcom: gpucc-sm8150: Add SC8180x support | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | warning | total: 0 errors, 2 warnings, 37 lines checked |
On Wed, 21 Jul 2021 15:53:29 -0700, Bjorn Andersson wrote: > The GPU clock controller found in SC8180x is a variant of the same block > found in SM8150, but with one additional clock frequency for the > gmu_clk_src clock. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- > .../devicetree/bindings/clock/qcom,gpucc.yaml | 1 + > drivers/clk/qcom/gpucc-sm8150.c | 12 ++++++++++++ > 2 files changed, 13 insertions(+) > Acked-by: Rob Herring <robh@kernel.org>
Quoting Bjorn Andersson (2021-07-21 15:53:29) > The GPU clock controller found in SC8180x is a variant of the same block > found in SM8150, but with one additional clock frequency for the > gmu_clk_src clock. > > Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> > --- Applied to clk-next
diff --git a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml index ecfe21284073..46dff46d5760 100644 --- a/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml +++ b/Documentation/devicetree/bindings/clock/qcom,gpucc.yaml @@ -26,6 +26,7 @@ properties: - qcom,sdm845-gpucc - qcom,sc7180-gpucc - qcom,sc7280-gpucc + - qcom,sc8180x-gpucc - qcom,sm8150-gpucc - qcom,sm8250-gpucc diff --git a/drivers/clk/qcom/gpucc-sm8150.c b/drivers/clk/qcom/gpucc-sm8150.c index 80fb6f73601d..8422fd047493 100644 --- a/drivers/clk/qcom/gpucc-sm8150.c +++ b/drivers/clk/qcom/gpucc-sm8150.c @@ -82,6 +82,14 @@ static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src[] = { { } }; +static const struct freq_tbl ftbl_gpu_cc_gmu_clk_src_sc8180x[] = { + F(19200000, P_BI_TCXO, 1, 0, 0), + F(200000000, P_GPLL0_OUT_MAIN_DIV, 1.5, 0, 0), + F(400000000, P_GPLL0_OUT_MAIN, 1.5, 0, 0), + F(500000000, P_GPU_CC_PLL1_OUT_MAIN, 1, 0, 0), + { } +}; + static struct clk_rcg2 gpu_cc_gmu_clk_src = { .cmd_rcgr = 0x1120, .mnd_width = 0, @@ -277,6 +285,7 @@ static const struct qcom_cc_desc gpu_cc_sm8150_desc = { }; static const struct of_device_id gpu_cc_sm8150_match_table[] = { + { .compatible = "qcom,sc8180x-gpucc" }, { .compatible = "qcom,sm8150-gpucc" }, { } }; @@ -290,6 +299,9 @@ static int gpu_cc_sm8150_probe(struct platform_device *pdev) if (IS_ERR(regmap)) return PTR_ERR(regmap); + if (of_device_is_compatible(pdev->dev.of_node, "qcom,sc8180x-gpucc")) + gpu_cc_gmu_clk_src.freq_tbl = ftbl_gpu_cc_gmu_clk_src_sc8180x; + clk_trion_pll_configure(&gpu_cc_pll1, regmap, &gpu_cc_pll1_config); return qcom_cc_really_probe(pdev, &gpu_cc_sm8150_desc, regmap);
The GPU clock controller found in SC8180x is a variant of the same block found in SM8150, but with one additional clock frequency for the gmu_clk_src clock. Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> --- .../devicetree/bindings/clock/qcom,gpucc.yaml | 1 + drivers/clk/qcom/gpucc-sm8150.c | 12 ++++++++++++ 2 files changed, 13 insertions(+)