diff mbox series

[v2,2/2] dt-bindings: clock: ad9545: Add documentation

Message ID 20210614070718.78041-3-alexandru.tachici@analog.com
State Changes Requested, archived
Headers show
Series clk: ad9545: Add support | expand

Checks

Context Check Description
robh/checkpatch success
robh/dt-meta-schema fail build log

Commit Message

Alexandru Tachici June 14, 2021, 7:07 a.m. UTC 
From: Alexandru Tachici <alexandru.tachici@analog.com>

Add dt bindings for ad9545.

Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>
---
 .../devicetree/bindings/clock/clk-ad9545.yaml | 556 ++++++++++++++++++
 include/dt-bindings/clock/ad9545.h            |  69 +++
 2 files changed, 625 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/clk-ad9545.yaml
 create mode 100644 include/dt-bindings/clock/ad9545.h

Comments

Rob Herring June 14, 2021, 1:39 p.m. UTC | #1 
On Mon, 14 Jun 2021 10:07:18 +0300, alexandru.tachici@analog.com wrote:
> From: Alexandru Tachici <alexandru.tachici@analog.com>
> 
> Add dt bindings for ad9545.
> 
> Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>
> ---
>  .../devicetree/bindings/clock/clk-ad9545.yaml | 556 ++++++++++++++++++
>  include/dt-bindings/clock/ad9545.h            |  69 +++
>  2 files changed, 625 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/clk-ad9545.yaml
>  create mode 100644 include/dt-bindings/clock/ad9545.h
> 

My bot found errors running 'make DT_CHECKER_FLAGS=-m dt_binding_check'
on your patch (DT_CHECKER_FLAGS is new in v5.13):

yamllint warnings/errors:
./Documentation/devicetree/bindings/clock/clk-ad9545.yaml:115:10: [warning] wrong indentation: expected 8 but found 9 (indentation)
./Documentation/devicetree/bindings/clock/clk-ad9545.yaml:118:10: [warning] wrong indentation: expected 8 but found 9 (indentation)
./Documentation/devicetree/bindings/clock/clk-ad9545.yaml:153:10: [warning] wrong indentation: expected 8 but found 9 (indentation)
./Documentation/devicetree/bindings/clock/clk-ad9545.yaml:156:10: [warning] wrong indentation: expected 8 but found 9 (indentation)
./Documentation/devicetree/bindings/clock/clk-ad9545.yaml:280:10: [warning] wrong indentation: expected 8 but found 9 (indentation)
./Documentation/devicetree/bindings/clock/clk-ad9545.yaml:283:10: [warning] wrong indentation: expected 8 but found 9 (indentation)
./Documentation/devicetree/bindings/clock/clk-ad9545.yaml:298:14: [warning] wrong indentation: expected 12 but found 13 (indentation)
./Documentation/devicetree/bindings/clock/clk-ad9545.yaml:301:14: [warning] wrong indentation: expected 12 but found 13 (indentation)
./Documentation/devicetree/bindings/clock/clk-ad9545.yaml:389:10: [warning] wrong indentation: expected 8 but found 9 (indentation)
./Documentation/devicetree/bindings/clock/clk-ad9545.yaml:392:10: [warning] wrong indentation: expected 8 but found 9 (indentation)
./Documentation/devicetree/bindings/clock/clk-ad9545.yaml:435:10: [warning] wrong indentation: expected 8 but found 9 (indentation)
./Documentation/devicetree/bindings/clock/clk-ad9545.yaml:438:10: [warning] wrong indentation: expected 8 but found 9 (indentation)

dtschema/dtc warnings/errors:
/builds/robherring/linux-dt-review/Documentation/devicetree/bindings/clock/clk-ad9545.example.dt.yaml: ad9545@4A: 'clocks' is a dependency of 'assigned-clocks'
	From schema: /usr/local/lib/python3.8/dist-packages/dtschema/schemas/clock/clock.yaml
\ndoc reference errors (make refcheckdocs):

See https://patchwork.ozlabs.org/patch/1491545

This check can fail if there are any dependencies. The base for a patch
series is generally the most recent rc1.

If you already ran 'make dt_binding_check' and didn't see the above
error(s), then make sure 'yamllint' is installed and dt-schema is up to
date:

pip3 install dtschema --upgrade

Please check and re-submit.
Rob Herring June 15, 2021, 10:50 p.m. UTC | #2 
On Mon, Jun 14, 2021 at 10:07:18AM +0300, alexandru.tachici@analog.com wrote:
> From: Alexandru Tachici <alexandru.tachici@analog.com>
> 
> Add dt bindings for ad9545.

Kind of a lot of properties, not really sure what to do about that...

> 
> Signed-off-by: Alexandru Tachici <alexandru.tachici@analog.com>
> ---
>  .../devicetree/bindings/clock/clk-ad9545.yaml | 556 ++++++++++++++++++
>  include/dt-bindings/clock/ad9545.h            |  69 +++
>  2 files changed, 625 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/clock/clk-ad9545.yaml
>  create mode 100644 include/dt-bindings/clock/ad9545.h
> 
> diff --git a/Documentation/devicetree/bindings/clock/clk-ad9545.yaml b/Documentation/devicetree/bindings/clock/clk-ad9545.yaml
> new file mode 100644
> index 000000000000..50553a88ab44
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/clock/clk-ad9545.yaml
> @@ -0,0 +1,556 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/clock/clk-ad9545.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: Analog Devices AD9545 Quad Input, 10-Output, Dual DPLL/IEEE 1588
> +
> +maintainers:
> +  - Alexandru Tachici <alexandru.tachici@analog.com>
> +
> +description: |
> +  Analog Devices AD9545 Quad Input, 10-Output, Dual DPLL/IEEE 1588,
> +  1 pps Synchronizer and Jitter Cleaner
> +  https://www.analog.com/media/en/technical-documentation/data-sheets/ADM1266.pdf
> +
> +properties:
> +  compatible:
> +    enum:
> +      - adi,ad9545
> +
> +  "#clock-cells":
> +    const: 2
> +
> +  reg:
> +    description: |

Don't need '|' if there's no formatting or anything that has to be 
escaped.

Same applies elsewhere.

> +      I2C address of the secondary device.
> +    minimum: 0
> +    maximum: 0xFF
> +
> +  avcc-supply:
> +    description: |
> +      Phandle to the Avcc power supply.
> +
> +  adi,freq-doubler:
> +    description: |
> +      The system clock PLL provides the user with the option of doubling the reference frequency.
> +    type: boolean
> +
> +  adi,ref-crystal:
> +    description: |
> +      At XOA,XOB there is a crystal connected that needs maintaining.
> +      Otherwise it is assumed that there is a TCXO or OCXO connected.
> +    type: boolean
> +
> +  adi,ref-frequency-hz:
> +    description: |
> +      Reference input frequency at XOA,XOB. This is used for the system clock.
> +
> +  clocks:
> +    items:
> +      - description: Ref A clock input
> +      - description: Ref AA clock input
> +      - description: Ref B clock input
> +      - description: Ref BB clock input
> +      - description: Ref M0 clock input
> +      - description: Ref M1 clock input
> +      - description: Ref M2 clock input
> +    maxItems: 4

Looks like 7 is the max...

> +
> +  assigned-clocks:
> +    description:
> +      Clocks are identified using two cells <&ad9545 clock_type clock_address>.
> +    minItems: 1
> +    maxItems: 14
> +
> +  assigned-clock-rates:
> +    minItems: 1
> +    maxItems: 14
> +
> +  assigned-clock-phases:
> +    minItems: 1
> +    maxItems: 14
> +
> +  clock-output-names:
> +    maxItems: 10
> +
> +  aux-dpll:
> +    description: |
> +      Auxiliary DPLL used for Closed-Loop method of system clock compensation.
> +    type: object
> +
> +    properties:
> +      adi,compensation-source:
> +        description: |
> +          System clock closed loop compensation source.
> +          Choose from Ref-A to Ref-BB [0-3] or aux TDCs [4-5].
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        enum: [0, 1, 2, 3, 4, 5]
> +
> +      adi,aux-dpll-bw-mhz:
> +        description: |
> +          Auxiliary DPLL bandwidth.
> +        minimum: 100
> +        maximum: 2000000
> +
> +      adi,rate-change-limit:
> +        description: |
> +          Error compensation rate change limiting expressed in ppb/s. Disabled if property is
> +          missing.
> +        $ref: /schemas/types.yaml#/definitions/uint32
> +        enum: [715, 1430, 2860, 5720, 11440, 22880, 45760]
> +
> +    required:
> +      - adi,compensation-source
> +      - adi,aux-dpll-bw-mhz
> +
> +  aux-tdc-clks:
> +    description: |
> +      Child nodes represent Mx pin reference clock inputs.
> +    type: object
> +
> +    properties:
> +      '#address-cells':
> +         const: 1
> +
> +      '#size-cells':
> +         const: 0
> +
> +    patternProperties:
> +      "^aux-tdc-clk@[0-3]$":
> +
> +        description: |
> +          Represents a Mx pin reference clock input.
> +        type: object
> +
> +        properties:
> +          reg:
> +            description: |
> +              Address of the Auxiliary TDC.
> +            maximum: 1

0-3 as the unit-address says or only 1? 

> +
> +          adi,pin-nr:
> +            description: |
> +              Pin number to be the source of this TDC.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 6
> +
> +        required:
> +          - reg
> +          - adi,pin-nr
> +
> +    additionalProperties: false
> +
> +  ref-input-clks:
> +    description: |
> +      Child nodes represent reference clock inputs.
> +    type: object
> +
> +    properties:
> +      '#address-cells':
> +         const: 1
> +
> +      '#size-cells':
> +         const: 0
> +
> +    patternProperties:
> +      "^ref-input-clk@[0-3]$":
> +        description: |
> +          Represents a reference clock input.
> +        type: object
> +
> +        properties:
> +          reg:
> +            description: |
> +              The reference input number. It can have up to 4 input clocks numbered from 0 to 3.
> +              (mapped: [refa, refaa, refb, refbb] -> [0, 1, 2, 3])
> +            maxItems: 1
> +
> +          adi,single-ended-mode:
> +            description: |
> +              Single-ended configuration mode.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            enum: [0, 1, 2, 3]
> +
> +          adi,differential-mode:
> +            description: |
> +              Differential configuration mode.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            enum: [0, 1, 2]
> +
> +          adi,r-divider-ratio:
> +            description: |
> +              Each reference input has a dedicated divider.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 1
> +            maximum: 1073741824
> +
> +          adi,ref-dtol-pbb:
> +            description: |
> +              REFx offset limit. Constitutes a fractional portion of the corresponding nominal period.
> +              The 24-bit number represents fractional units of parts per billion (ppb) up to a
> +              maximum of approximately 17 million ppb (1.7%).
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 16777215
> +            default: 100000
> +
> +          adi,ref-monitor-hysteresis-pbb:
> +            description: |
> +              Basis points of the offset limit representing per ten thousand of REFx offset limit.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            enum: [0, 3125, 6250, 12500, 25000, 50000, 75000, 87500]
> +            default: 12500
> +
> +          adi,ref-validation-timer-ms:
> +            description: |
> +              Time required for a reference to remain in tolerance condition before being
> +              available to be used.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 1
> +            maximum: 1048574
> +            default: 10
> +
> +          adi,freq-lock-threshold-ps:
> +            description: |
> +              Phase lock detector threshold (in picoseconds).
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 1
> +            maximum: 16777215
> +
> +          adi,phase-lock-threshold-ps:
> +            description: |
> +              Profile 0 frequency lock threshold. Frequency lock detector threshold (in picoseconds).
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 1
> +            maximum: 16777215
> +
> +          adi,phase-lock-fill-rate:
> +            description: |
> +              Parameter used by the DPLL Phase Lock Detector.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 1
> +            maximum: 255
> +            default: 10
> +
> +          adi,phase-lock-drain-rate:
> +            description: |
> +              Parameter used by the DPLL Phase Lock Detector.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 1
> +            maximum: 255
> +            default: 10
> +
> +          adi,freq-lock-fill-rate:
> +            description: |
> +              Parameter used by the DPLL Frequency Lock Detector.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 1
> +            maximum: 255
> +            default: 10
> +
> +          adi,freq-lock-drain-rate:
> +            description: |
> +              Parameter used by the DPLL Frequency Lock Detector.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 1
> +            maximum: 255
> +            default: 10
> +
> +        required:
> +          - reg
> +          - adi,r-divider-ratio
> +          - adi,ref-dtol-pbb
> +          - adi,ref-monitor-hysteresis-pbb
> +          - adi,ref-validation-timer-ms
> +          - adi,freq-lock-threshold-ps
> +          - adi,phase-lock-threshold-ps
> +
> +    additionalProperties: false
> +
> +  pll-clks:
> +    description: |
> +      Child nodes represent PLLs.
> +    type: object
> +
> +    properties:
> +      '#address-cells':
> +         const: 1
> +
> +      '#size-cells':
> +         const: 0
> +
> +    patternProperties:
> +      "^pll-clk@[0-1]$":
> +        description: |
> +          Represents a PLL.
> +        type: object
> +
> +        properties:
> +          reg:
> +            description: |
> +              PLL number. AD9545 has two PLLs.
> +            maxItems: 1
> +
> +          '#address-cells':
> +             const: 1
> +
> +          '#size-cells':
> +             const: 0
> +
> +          adi,fast-acq-trigger-mode:
> +            description: |
> +              If this is not specified Fast Acquisition will be used every time. See reg 0x2106
> +              for constraints on Fast Acquisition trigger.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 0
> +            maximum: 15
> +            default: 0
> +
> +        patternProperties:
> +          "^profile@[0-5]$":
> +            description: |
> +              Represents a DPLL profile. Each DPLL can have up to 6 specified sources
> +              wih priorities assigned.
> +            type: object
> +
> +            properties:
> +              reg:
> +                description: |
> +                  Profile number. A DPLL can have up to 6 translation profiles.
> +                maxItems: 1

Blank line

> +              adi,profile-priority:
> +                description: |
> +                  Profile selection priority. 0 is the highest, 31 is the lowest. For revertive
> +                  reference switching, ensure that priority difference is > 7.
> +                $ref: /schemas/types.yaml#/definitions/uint32
> +                minimum: 0
> +                maximum: 31
> +
> +              adi,pll-source:
> +                description: |
> +                  Each PLL can have 1 signal source. Choose from Ref-A to Ref-BB [0-3] or aux NCOs [4-5].
> +                $ref: /schemas/types.yaml#/definitions/uint32
> +                enum: [0, 1, 2, 3, 4, 5]
> +
> +              adi,pll-loop-bandwidth-uhz:
> +                description: |
> +                  PLL loop bandwidth in microhertz.
> +                $ref: /schemas/types.yaml#/definitions/uint32
> +                minimum: 1
> +                maximum: 1850000000
> +                default: 200000000
> +
> +              adi,fast-acq-excess-bw:
> +                description: |
> +                  Controls the DPLL loop bandwidth scaling factor while in fast acquisition mode.
> +                  0 means this feature is disabled.
> +                $ref: /schemas/types.yaml#/definitions/uint32
> +                enum: [0, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024]
> +                default: 0
> +
> +              adi,fast-acq-timeout-ms:
> +                description: |
> +                  Fast acquisition timeout controls the maximum amount of time that DPLL waits to
> +                  achieve phase lock before reducing the loop bandwidth by a factor of two.
> +                $ref: /schemas/types.yaml#/definitions/uint32
> +                enum: [1, 10, 50, 100, 500, 1000, 10000, 50000]
> +                default: 1
> +
> +              adi,fast-acq-lock-settle-ms:
> +                description: |
> +                  Controls how long DPLL must wait after achieving phase lock before reducing
> +                  the loop bandwidth by a factor of 2.
> +                $ref: /schemas/types.yaml#/definitions/uint32
> +                enum: [1, 10, 50, 100, 500, 1000, 10000, 50000]
> +                default: 1
> +
> +            required:
> +              - reg
> +              - adi,pll-source
> +              - adi,pll-loop-bandwidth-uhz
> +
> +        additionalProperties: false
> +
> +        required:
> +          - reg
> +
> +    additionalProperties: false
> +
> +  aux-ncos:
> +    description: |
> +      Child nodes represent auxiliary Numerical Controlled Oscilators.
> +    type: object
> +
> +    properties:
> +      '#address-cells':
> +         const: 1
> +
> +      '#size-cells':
> +         const: 0
> +
> +    patternProperties:
> +      "^aux-nco-clk@[0-1]$":
> +        description: |
> +          Represents an auxiliary Numerical Controlled Oscilator. Generates timestamps that
> +          can be sent to the DPLL0 or DPLL1.
> +        type: object
> +
> +        properties:
> +          reg:
> +            description: |
> +              Auxiliary NCO address mapped: [NCO0, NCO1] -> [0, 1].
> +            maxItems: 1
> +
> +          adi,freq-lock-threshold-ps:
> +            description: |
> +              Phase lock detector threshold (in picoseconds).
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 1
> +            maximum: 16777215
> +
> +          adi,phase-lock-threshold-ps:
> +            description: |
> +              Profile 0 frequency lock threshold. Frequency lock detector threshold (in picoseconds).
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            minimum: 1
> +            maximum: 16777215
> +
> +        required:
> +          - reg
> +          - adi,freq-lock-threshold-ps
> +          - adi,phase-lock-threshold-ps
> +
> +    additionalProperties: false
> +
> +  output-clks:
> +    description: |
> +      Child nodes represent clock outputs.
> +    type: object
> +
> +    properties:
> +      '#address-cells':
> +         const: 1
> +
> +      '#size-cells':
> +         const: 0
> +
> +    patternProperties:
> +      "^output-clk@([0-9]|1[0-3])$":
> +        description: |
> +          Represents a clock output.
> +        type: object
> +
> +        properties:
> +          reg:
> +            description: |
> +              The reference input number. It can have up to 10 output clocks mapped:
> +              (OUT0AP OUT0AN OUT0BP OUT0BN OUT0CP OUT0CN OUT1AP OUT1AN OUT1BP OUT1BN) ->
> +              (0, 1, 2, 3, 4, 5, 6, 7, 8, 9)

Looks like constraints (maximum: 9).

> +            maxItems: 1
> +
> +          adi,current-source:
> +            description: |
> +              If specified output is set as current source.
> +            type: boolean
> +
> +          adi,current-source-microamp:
> +            description: |
> +              The magnitude of the driver current.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            enum: [7500, 12500, 15000]
> +
> +          adi,output-mode:
> +            description: |
> +              Output driver mode.
> +            $ref: /schemas/types.yaml#/definitions/uint32
> +            enum: [0, 1, 2]
> +
> +        required:
> +          - reg
> +          - adi,current-source-microamp
> +          - adi,output-mode
> +
> +    additionalProperties: false
> +
> +required:
> +  - compatible
> +  - reg
> +  - adi,ref-frequency-hz
> +
> +additionalProperties: false
> +
> +examples:
> +  - |
> +    #include <dt-bindings/clock/ad9545.h>
> +
> +    i2c1 {

i2c {

> +        #address-cells = <1>;
> +        #size-cells = <0>;
> +
> +        ad9545_clock: ad9545@4A {

clock-controller@4a

> +                compatible = "adi,ad9545";
> +                reg = <0x4A>;
> +
> +                adi,ref-crystal;
> +                adi,ref-frequency-hz = <52000000>;
> +
> +                #clock-cells = <2>;
> +                assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
> +                                  <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
> +                                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
> +                                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1B>;
> +                assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
> +                assigned-clock-phases = <0>, <0>, <0>, <180>;
> +
> +                aux-ncos {
> +                        #address-cells = <1>;
> +                        #size-cells = <0>;
> +
> +                        aux-nco-clk@AD9545_NCO0 {

Can't have defines in unit addresses. We generally don't have defines 
for 'reg' values.

> +                                reg = <AD9545_NCO0>;
> +                                adi,freq-lock-threshold-ps = <16000000>;
> +                                adi,phase-lock-threshold-ps = <16000000>;
> +                        };
> +                };
> +
> +                pll-clks {
> +                        #address-cells = <1>;
> +                        #size-cells = <0>;
> +
> +                        ad9545_apll1: pll-clk@AD9545_PLL1 {
> +                                reg = <AD9545_PLL1>;
> +
> +                                #address-cells = <1>;
> +                                #size-cells = <0>;
> +
> +                                profile@0 {
> +                                       reg = <0>;
> +                                       adi,pll-source = <4>;
> +                                       adi,profile-priority = <0>;
> +                                       adi,pll-loop-bandwidth-uhz = <200000000>;
> +                                };
> +                        };
> +                };
> +
> +                output-clks {
> +                        #address-cells = <1>;
> +                        #size-cells = <0>;
> +
> +                        output-clk@AD9545_Q1A {
> +                                reg = <AD9545_Q1A>;
> +                                adi,output-mode = <DRIVER_MODE_DUAL_DIV>;
> +                                adi,current-source-microamp = <15000>;
> +                        };
> +
> +                        output-clk@AD9545_Q1B {
> +                                reg = <AD9545_Q1B>;
> +                                adi,output-mode = <DRIVER_MODE_DUAL_DIV>;
> +                                adi,current-source-microamp = <15000>;
> +                        };
> +                };
> +        };
> +    };
> +...
> diff --git a/include/dt-bindings/clock/ad9545.h b/include/dt-bindings/clock/ad9545.h
> new file mode 100644
> index 000000000000..857d50e5715b
> --- /dev/null
> +++ b/include/dt-bindings/clock/ad9545.h
> @@ -0,0 +1,69 @@
> +/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
> +/*
> + * AD9545 Network Clock Generator/Synchronizer
> + *
> + * Copyright 2020 Analog Devices Inc.
> + */
> +
> +#ifndef _DT_BINDINGS_CLOCK_AD9545_H_
> +#define _DT_BINDINGS_CLOCK_AD9545_H_
> +
> +/* Input Driver Mode
> + * Use for adi,single-ended-mode:
> + */
> +#define DRIVER_MODE_AC_COUPLED_IF	0
> +#define DRIVER_MODE_DC_COUPLED_1V2	1
> +#define DRIVER_MODE_DC_COUPLED_1V8	2
> +#define DRIVER_MODE_IN_PULL_UP		3
> +
> +/* Input Driver Mode
> + * Use for adi,differential-mode:
> + */
> +#define DRIVER_MODE_AC_COUPLED		0
> +#define DRIVER_MODE_DC_COUPLED		1
> +#define DRIVER_MODE_DC_COUPLED_LVDS	2
> +
> +/* Output Driver Mode
> + * Use for adi,output-mode:
> + */
> +#define DRIVER_MODE_SINGLE_DIV_DIF	0
> +#define DRIVER_MODE_SINGLE_DIV		1
> +#define DRIVER_MODE_DUAL_DIV		2
> +
> +/* Clock types */
> +#define AD9545_CLK_OUT			0
> +#define AD9545_CLK_PLL			1
> +#define AD9545_CLK_NCO			2
> +#define AD9545_CLK_AUX_TDC		3
> +
> +/* PLL addresses */
> +#define AD9545_PLL0			0
> +#define AD9545_PLL1			1
> +
> +/* Outputs addresses */
> +#define AD9545_Q0A			0
> +#define AD9545_Q0AA			1
> +#define AD9545_Q0B			2
> +#define AD9545_Q0BB			3
> +#define AD9545_Q0C			4
> +#define AD9545_Q0CC			5
> +#define AD9545_Q1A			6
> +#define AD9545_Q1AA			7
> +#define AD9545_Q1B			8
> +#define AD9545_Q1BB			9
> +
> +/* NCO addresses */
> +#define AD9545_NCO0			0
> +#define AD9545_NCO1			1
> +
> +/* TDC addresses */
> +#define AD9545_CLK_AUX_TDC0		0
> +#define AD9545_CLK_AUX_TDC1		1
> +
> +/* Ex:
> + * Output Q0C clock: <&ad9545_clock AD9545_CLK_OUT AD9545_Q0C>;
> + * PLL0 clock: <&ad9545_clock AD9545_CLK_PLL AD9545_PLL0>;
> + * NCO1 clock: <&ad9545_clock AD9545_CLK_NCO AD9545_NCO1>;
> + */
> +
> +#endif /* _DT_BINDINGS_CLOCK_AD9545_H_ */
> -- 
> 2.25.1
kernel test robot June 16, 2021, 6:53 p.m. UTC | #3 
Hi,

I love your patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on robh/for-next linux/master linus/master v5.13-rc6 next-20210616]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/alexandru-tachici-analog-com/clk-ad9545-Add-support/20210616-153412
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: m68k-allmodconfig (attached as .config)
compiler: m68k-linux-gcc (GCC) 9.3.0
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # https://github.com/0day-ci/linux/commit/b46755cf562ff8a1a9841a4560e344099f3f054e
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review alexandru-tachici-analog-com/clk-ad9545-Add-support/20210616-153412
        git checkout b46755cf562ff8a1a9841a4560e344099f3f054e
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross ARCH=m68k 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/clk/adi/clk-ad9545.c:2402:5: warning: no previous prototype for 'ad9545_probe' [-Wmissing-prototypes]
    2402 | int ad9545_probe(struct device *dev, struct regmap *regmap)
         |     ^~~~~~~~~~~~


vim +/ad9545_probe +2402 drivers/clk/adi/clk-ad9545.c

f88d17c990b731 Alexandru Tachici 2021-06-14  2401  
f88d17c990b731 Alexandru Tachici 2021-06-14 @2402  int ad9545_probe(struct device *dev, struct regmap *regmap)
f88d17c990b731 Alexandru Tachici 2021-06-14  2403  {
f88d17c990b731 Alexandru Tachici 2021-06-14  2404  	struct ad9545_state *st;
f88d17c990b731 Alexandru Tachici 2021-06-14  2405  	int ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  2406  
f88d17c990b731 Alexandru Tachici 2021-06-14  2407  	st = devm_kzalloc(dev, sizeof(struct ad9545_state), GFP_KERNEL);
f88d17c990b731 Alexandru Tachici 2021-06-14  2408  	if (!st)
f88d17c990b731 Alexandru Tachici 2021-06-14  2409  		return -ENOMEM;
f88d17c990b731 Alexandru Tachici 2021-06-14  2410  
f88d17c990b731 Alexandru Tachici 2021-06-14  2411  	st->dev = dev;
f88d17c990b731 Alexandru Tachici 2021-06-14  2412  	st->regmap = regmap;
f88d17c990b731 Alexandru Tachici 2021-06-14  2413  
f88d17c990b731 Alexandru Tachici 2021-06-14  2414  	ret = ad9545_check_id(st);
f88d17c990b731 Alexandru Tachici 2021-06-14  2415  	if (ret < 0)
f88d17c990b731 Alexandru Tachici 2021-06-14  2416  		return ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  2417  
f88d17c990b731 Alexandru Tachici 2021-06-14  2418  	ret = ad9545_parse_dt(st);
f88d17c990b731 Alexandru Tachici 2021-06-14  2419  	if (ret < 0)
f88d17c990b731 Alexandru Tachici 2021-06-14  2420  		return ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  2421  
f88d17c990b731 Alexandru Tachici 2021-06-14  2422  	return ad9545_setup(st);
f88d17c990b731 Alexandru Tachici 2021-06-14  2423  }
f88d17c990b731 Alexandru Tachici 2021-06-14  2424  EXPORT_SYMBOL_GPL(ad9545_probe);
f88d17c990b731 Alexandru Tachici 2021-06-14  2425  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
kernel test robot June 17, 2021, 7:55 a.m. UTC | #4 
Hi,

I love your patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on robh/for-next linux/master linus/master v5.13-rc6 next-20210616]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/alexandru-tachici-analog-com/clk-ad9545-Add-support/20210616-153412
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: i386-randconfig-s032-20210617 (attached as .config)
compiler: gcc-9 (Debian 9.3.0-22) 9.3.0
reproduce:
        # apt-get install sparse
        # sparse version: v0.6.3-341-g8af24329-dirty
        # https://github.com/0day-ci/linux/commit/b46755cf562ff8a1a9841a4560e344099f3f054e
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review alexandru-tachici-analog-com/clk-ad9545-Add-support/20210616-153412
        git checkout b46755cf562ff8a1a9841a4560e344099f3f054e
        # save the attached .config to linux build tree
        make W=1 C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=i386 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>


sparse warnings: (new ones prefixed by >>)
>> drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: cast from restricted __le32
>> drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: restricted __le32 degrades to integer
>> drivers/clk/adi/clk-ad9545.c:1407:24: sparse: sparse: incorrect type in assignment (different base types) @@     expected restricted __le32 [addressable] [assigned] [usertype] regval @@     got unsigned int freq_lock_fill_rate @@
   drivers/clk/adi/clk-ad9545.c:1407:24: sparse:     expected restricted __le32 [addressable] [assigned] [usertype] regval
   drivers/clk/adi/clk-ad9545.c:1407:24: sparse:     got unsigned int freq_lock_fill_rate
>> drivers/clk/adi/clk-ad9545.c:1409:88: sparse: sparse: incorrect type in argument 3 (different base types) @@     expected unsigned int val @@     got restricted __le32 [addressable] [assigned] [usertype] regval @@
   drivers/clk/adi/clk-ad9545.c:1409:88: sparse:     expected unsigned int val
   drivers/clk/adi/clk-ad9545.c:1409:88: sparse:     got restricted __le32 [addressable] [assigned] [usertype] regval
>> drivers/clk/adi/clk-ad9545.c:1414:24: sparse: sparse: incorrect type in assignment (different base types) @@     expected restricted __le32 [addressable] [assigned] [usertype] regval @@     got unsigned int freq_lock_drain_rate @@
   drivers/clk/adi/clk-ad9545.c:1414:24: sparse:     expected restricted __le32 [addressable] [assigned] [usertype] regval
   drivers/clk/adi/clk-ad9545.c:1414:24: sparse:     got unsigned int freq_lock_drain_rate
   drivers/clk/adi/clk-ad9545.c:1416:89: sparse: sparse: incorrect type in argument 3 (different base types) @@     expected unsigned int val @@     got restricted __le32 [addressable] [assigned] [usertype] regval @@
   drivers/clk/adi/clk-ad9545.c:1416:89: sparse:     expected unsigned int val
   drivers/clk/adi/clk-ad9545.c:1416:89: sparse:     got restricted __le32 [addressable] [assigned] [usertype] regval
>> drivers/clk/adi/clk-ad9545.c:1421:24: sparse: sparse: incorrect type in assignment (different base types) @@     expected restricted __le32 [addressable] [assigned] [usertype] regval @@     got unsigned int phase_lock_fill_rate @@
   drivers/clk/adi/clk-ad9545.c:1421:24: sparse:     expected restricted __le32 [addressable] [assigned] [usertype] regval
   drivers/clk/adi/clk-ad9545.c:1421:24: sparse:     got unsigned int phase_lock_fill_rate
   drivers/clk/adi/clk-ad9545.c:1423:89: sparse: sparse: incorrect type in argument 3 (different base types) @@     expected unsigned int val @@     got restricted __le32 [addressable] [assigned] [usertype] regval @@
   drivers/clk/adi/clk-ad9545.c:1423:89: sparse:     expected unsigned int val
   drivers/clk/adi/clk-ad9545.c:1423:89: sparse:     got restricted __le32 [addressable] [assigned] [usertype] regval
>> drivers/clk/adi/clk-ad9545.c:1428:24: sparse: sparse: incorrect type in assignment (different base types) @@     expected restricted __le32 [addressable] [assigned] [usertype] regval @@     got unsigned int phase_lock_drain_rate @@
   drivers/clk/adi/clk-ad9545.c:1428:24: sparse:     expected restricted __le32 [addressable] [assigned] [usertype] regval
   drivers/clk/adi/clk-ad9545.c:1428:24: sparse:     got unsigned int phase_lock_drain_rate
   drivers/clk/adi/clk-ad9545.c:1430:90: sparse: sparse: incorrect type in argument 3 (different base types) @@     expected unsigned int val @@     got restricted __le32 [addressable] [assigned] [usertype] regval @@
   drivers/clk/adi/clk-ad9545.c:1430:90: sparse:     expected unsigned int val
   drivers/clk/adi/clk-ad9545.c:1430:90: sparse:     got restricted __le32 [addressable] [assigned] [usertype] regval

vim +1114 drivers/clk/adi/clk-ad9545.c

f88d17c990b731 Alexandru Tachici 2021-06-14  1089  
f88d17c990b731 Alexandru Tachici 2021-06-14  1090  static int ad9545_out_clk_get_phase(struct clk_hw *hw)
f88d17c990b731 Alexandru Tachici 2021-06-14  1091  {
f88d17c990b731 Alexandru Tachici 2021-06-14  1092  	struct ad9545_out_clk *clk = to_out_clk(hw);
f88d17c990b731 Alexandru Tachici 2021-06-14  1093  	u64 input_edges_nr;
f88d17c990b731 Alexandru Tachici 2021-06-14  1094  	u64 phase_code;
f88d17c990b731 Alexandru Tachici 2021-06-14  1095  	__le32 regval;
f88d17c990b731 Alexandru Tachici 2021-06-14  1096  	u32 phase_conf;
f88d17c990b731 Alexandru Tachici 2021-06-14  1097  	u32 qdiv;
f88d17c990b731 Alexandru Tachici 2021-06-14  1098  	int ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  1099  
f88d17c990b731 Alexandru Tachici 2021-06-14  1100  	ret = ad9545_get_q_div(clk->st, clk->address, &qdiv);
f88d17c990b731 Alexandru Tachici 2021-06-14  1101  	if (ret < 0)
f88d17c990b731 Alexandru Tachici 2021-06-14  1102  		return ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  1103  
f88d17c990b731 Alexandru Tachici 2021-06-14  1104  	ret = regmap_read(clk->st->regmap, AD9545_QX_PHASE_CONF(clk->address), &phase_conf);
f88d17c990b731 Alexandru Tachici 2021-06-14  1105  	if (ret < 0)
f88d17c990b731 Alexandru Tachici 2021-06-14  1106  		return ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  1107  
f88d17c990b731 Alexandru Tachici 2021-06-14  1108  	ret = regmap_bulk_read(clk->st->regmap, AD9545_QX_PHASE(clk->address), &regval, 4);
f88d17c990b731 Alexandru Tachici 2021-06-14  1109  	if (ret < 0)
f88d17c990b731 Alexandru Tachici 2021-06-14  1110  		return ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  1111  
f88d17c990b731 Alexandru Tachici 2021-06-14  1112  	/* Qxy phase bitfield is 33 bits long, with last bit in PHASE_CONF reg */
f88d17c990b731 Alexandru Tachici 2021-06-14  1113  	phase_code = !!(phase_conf & AD9545_QX_PHASE_32_MSK);
f88d17c990b731 Alexandru Tachici 2021-06-14 @1114  	phase_code = (phase_code >> 32) + cpu_to_le32(regval);
f88d17c990b731 Alexandru Tachici 2021-06-14  1115  
f88d17c990b731 Alexandru Tachici 2021-06-14  1116  	input_edges_nr = 2 * qdiv + !!(phase_conf & AD9545_QX_HALF_DIV_MSK);
f88d17c990b731 Alexandru Tachici 2021-06-14  1117  
f88d17c990b731 Alexandru Tachici 2021-06-14  1118  	/*
f88d17c990b731 Alexandru Tachici 2021-06-14  1119  	 * phase = 360 * (Qxy Phase / E) where:
f88d17c990b731 Alexandru Tachici 2021-06-14  1120  	 * E is the total number of input edges per output period of the Q-divider.
f88d17c990b731 Alexandru Tachici 2021-06-14  1121  	 */
f88d17c990b731 Alexandru Tachici 2021-06-14  1122  	return div64_u64(phase_code * 360, input_edges_nr);
f88d17c990b731 Alexandru Tachici 2021-06-14  1123  }
f88d17c990b731 Alexandru Tachici 2021-06-14  1124  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
kernel test robot June 18, 2021, 4:17 a.m. UTC | #5 
Hi,

I love your patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on robh/for-next linux/master linus/master v5.13-rc6 next-20210617]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/alexandru-tachici-analog-com/clk-ad9545-Add-support/20210616-153412
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: h8300-randconfig-s031-20210618 (attached as .config)
compiler: h8300-linux-gcc (GCC) 9.3.0
reproduce:
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # apt-get install sparse
        # sparse version: v0.6.3-341-g8af24329-dirty
        # https://github.com/0day-ci/linux/commit/b46755cf562ff8a1a9841a4560e344099f3f054e
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review alexandru-tachici-analog-com/clk-ad9545-Add-support/20210616-153412
        git checkout b46755cf562ff8a1a9841a4560e344099f3f054e
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-9.3.0 make.cross C=1 CF='-fdiagnostic-prefix -D__CHECK_ENDIAN__' W=1 ARCH=h8300 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>


sparse warnings: (new ones prefixed by >>)
   drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: cast from restricted __le32
>> drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: incorrect type in argument 1 (different base types) @@     expected unsigned int [usertype] val @@     got restricted __le32 [addressable] [usertype] regval @@
   drivers/clk/adi/clk-ad9545.c:1114:43: sparse:     expected unsigned int [usertype] val
   drivers/clk/adi/clk-ad9545.c:1114:43: sparse:     got restricted __le32 [addressable] [usertype] regval
   drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: cast from restricted __le32
   drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: cast from restricted __le32
   drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: cast from restricted __le32
   drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: cast from restricted __le32
   drivers/clk/adi/clk-ad9545.c:1114:43: sparse: sparse: restricted __le32 degrades to integer
   drivers/clk/adi/clk-ad9545.c:1407:24: sparse: sparse: incorrect type in assignment (different base types) @@     expected restricted __le32 [addressable] [assigned] [usertype] regval @@     got unsigned int freq_lock_fill_rate @@
   drivers/clk/adi/clk-ad9545.c:1407:24: sparse:     expected restricted __le32 [addressable] [assigned] [usertype] regval
   drivers/clk/adi/clk-ad9545.c:1407:24: sparse:     got unsigned int freq_lock_fill_rate
   drivers/clk/adi/clk-ad9545.c:1409:88: sparse: sparse: incorrect type in argument 3 (different base types) @@     expected unsigned int val @@     got restricted __le32 [addressable] [assigned] [usertype] regval @@
   drivers/clk/adi/clk-ad9545.c:1409:88: sparse:     expected unsigned int val
   drivers/clk/adi/clk-ad9545.c:1409:88: sparse:     got restricted __le32 [addressable] [assigned] [usertype] regval
   drivers/clk/adi/clk-ad9545.c:1414:24: sparse: sparse: incorrect type in assignment (different base types) @@     expected restricted __le32 [addressable] [assigned] [usertype] regval @@     got unsigned int freq_lock_drain_rate @@
   drivers/clk/adi/clk-ad9545.c:1414:24: sparse:     expected restricted __le32 [addressable] [assigned] [usertype] regval
   drivers/clk/adi/clk-ad9545.c:1414:24: sparse:     got unsigned int freq_lock_drain_rate
   drivers/clk/adi/clk-ad9545.c:1416:89: sparse: sparse: incorrect type in argument 3 (different base types) @@     expected unsigned int val @@     got restricted __le32 [addressable] [assigned] [usertype] regval @@
   drivers/clk/adi/clk-ad9545.c:1416:89: sparse:     expected unsigned int val
   drivers/clk/adi/clk-ad9545.c:1416:89: sparse:     got restricted __le32 [addressable] [assigned] [usertype] regval
   drivers/clk/adi/clk-ad9545.c:1421:24: sparse: sparse: incorrect type in assignment (different base types) @@     expected restricted __le32 [addressable] [assigned] [usertype] regval @@     got unsigned int phase_lock_fill_rate @@
   drivers/clk/adi/clk-ad9545.c:1421:24: sparse:     expected restricted __le32 [addressable] [assigned] [usertype] regval
   drivers/clk/adi/clk-ad9545.c:1421:24: sparse:     got unsigned int phase_lock_fill_rate
   drivers/clk/adi/clk-ad9545.c:1423:89: sparse: sparse: incorrect type in argument 3 (different base types) @@     expected unsigned int val @@     got restricted __le32 [addressable] [assigned] [usertype] regval @@
   drivers/clk/adi/clk-ad9545.c:1423:89: sparse:     expected unsigned int val
   drivers/clk/adi/clk-ad9545.c:1423:89: sparse:     got restricted __le32 [addressable] [assigned] [usertype] regval
   drivers/clk/adi/clk-ad9545.c:1428:24: sparse: sparse: incorrect type in assignment (different base types) @@     expected restricted __le32 [addressable] [assigned] [usertype] regval @@     got unsigned int phase_lock_drain_rate @@
   drivers/clk/adi/clk-ad9545.c:1428:24: sparse:     expected restricted __le32 [addressable] [assigned] [usertype] regval
   drivers/clk/adi/clk-ad9545.c:1428:24: sparse:     got unsigned int phase_lock_drain_rate
   drivers/clk/adi/clk-ad9545.c:1430:90: sparse: sparse: incorrect type in argument 3 (different base types) @@     expected unsigned int val @@     got restricted __le32 [addressable] [assigned] [usertype] regval @@
   drivers/clk/adi/clk-ad9545.c:1430:90: sparse:     expected unsigned int val
   drivers/clk/adi/clk-ad9545.c:1430:90: sparse:     got restricted __le32 [addressable] [assigned] [usertype] regval

vim +1114 drivers/clk/adi/clk-ad9545.c

f88d17c990b731 Alexandru Tachici 2021-06-14  1089  
f88d17c990b731 Alexandru Tachici 2021-06-14  1090  static int ad9545_out_clk_get_phase(struct clk_hw *hw)
f88d17c990b731 Alexandru Tachici 2021-06-14  1091  {
f88d17c990b731 Alexandru Tachici 2021-06-14  1092  	struct ad9545_out_clk *clk = to_out_clk(hw);
f88d17c990b731 Alexandru Tachici 2021-06-14  1093  	u64 input_edges_nr;
f88d17c990b731 Alexandru Tachici 2021-06-14  1094  	u64 phase_code;
f88d17c990b731 Alexandru Tachici 2021-06-14  1095  	__le32 regval;
f88d17c990b731 Alexandru Tachici 2021-06-14  1096  	u32 phase_conf;
f88d17c990b731 Alexandru Tachici 2021-06-14  1097  	u32 qdiv;
f88d17c990b731 Alexandru Tachici 2021-06-14  1098  	int ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  1099  
f88d17c990b731 Alexandru Tachici 2021-06-14  1100  	ret = ad9545_get_q_div(clk->st, clk->address, &qdiv);
f88d17c990b731 Alexandru Tachici 2021-06-14  1101  	if (ret < 0)
f88d17c990b731 Alexandru Tachici 2021-06-14  1102  		return ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  1103  
f88d17c990b731 Alexandru Tachici 2021-06-14  1104  	ret = regmap_read(clk->st->regmap, AD9545_QX_PHASE_CONF(clk->address), &phase_conf);
f88d17c990b731 Alexandru Tachici 2021-06-14  1105  	if (ret < 0)
f88d17c990b731 Alexandru Tachici 2021-06-14  1106  		return ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  1107  
f88d17c990b731 Alexandru Tachici 2021-06-14  1108  	ret = regmap_bulk_read(clk->st->regmap, AD9545_QX_PHASE(clk->address), &regval, 4);
f88d17c990b731 Alexandru Tachici 2021-06-14  1109  	if (ret < 0)
f88d17c990b731 Alexandru Tachici 2021-06-14  1110  		return ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  1111  
f88d17c990b731 Alexandru Tachici 2021-06-14  1112  	/* Qxy phase bitfield is 33 bits long, with last bit in PHASE_CONF reg */
f88d17c990b731 Alexandru Tachici 2021-06-14  1113  	phase_code = !!(phase_conf & AD9545_QX_PHASE_32_MSK);
f88d17c990b731 Alexandru Tachici 2021-06-14 @1114  	phase_code = (phase_code >> 32) + cpu_to_le32(regval);
f88d17c990b731 Alexandru Tachici 2021-06-14  1115  
f88d17c990b731 Alexandru Tachici 2021-06-14  1116  	input_edges_nr = 2 * qdiv + !!(phase_conf & AD9545_QX_HALF_DIV_MSK);
f88d17c990b731 Alexandru Tachici 2021-06-14  1117  
f88d17c990b731 Alexandru Tachici 2021-06-14  1118  	/*
f88d17c990b731 Alexandru Tachici 2021-06-14  1119  	 * phase = 360 * (Qxy Phase / E) where:
f88d17c990b731 Alexandru Tachici 2021-06-14  1120  	 * E is the total number of input edges per output period of the Q-divider.
f88d17c990b731 Alexandru Tachici 2021-06-14  1121  	 */
f88d17c990b731 Alexandru Tachici 2021-06-14  1122  	return div64_u64(phase_code * 360, input_edges_nr);
f88d17c990b731 Alexandru Tachici 2021-06-14  1123  }
f88d17c990b731 Alexandru Tachici 2021-06-14  1124  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
kernel test robot June 22, 2021, 7:02 a.m. UTC | #6 
Hi,

I love your patch! Perhaps something to improve:

[auto build test WARNING on clk/clk-next]
[also build test WARNING on robh/for-next linux/master linus/master v5.13-rc7 next-20210621]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/0day-ci/linux/commits/alexandru-tachici-analog-com/clk-ad9545-Add-support/20210616-153412
base:   https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: x86_64-randconfig-r005-20210622 (attached as .config)
compiler: clang version 13.0.0 (https://github.com/llvm/llvm-project b3634d3e88b7f26534a5057bff182b7dced584fc)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install x86_64 cross compiling tool for clang build
        # apt-get install binutils-x86-64-linux-gnu
        # https://github.com/0day-ci/linux/commit/b46755cf562ff8a1a9841a4560e344099f3f054e
        git remote add linux-review https://github.com/0day-ci/linux
        git fetch --no-tags linux-review alexandru-tachici-analog-com/clk-ad9545-Add-support/20210616-153412
        git checkout b46755cf562ff8a1a9841a4560e344099f3f054e
        # save the attached .config to linux build tree
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross ARCH=x86_64 

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

>> drivers/clk/adi/clk-ad9545.c:2402:5: warning: no previous prototype for function 'ad9545_probe' [-Wmissing-prototypes]
   int ad9545_probe(struct device *dev, struct regmap *regmap)
       ^
   drivers/clk/adi/clk-ad9545.c:2402:1: note: declare 'static' if the function is not intended to be used outside of this translation unit
   int ad9545_probe(struct device *dev, struct regmap *regmap)
   ^
   static 
   1 warning generated.


vim +/ad9545_probe +2402 drivers/clk/adi/clk-ad9545.c

f88d17c990b731 Alexandru Tachici 2021-06-14  2401  
f88d17c990b731 Alexandru Tachici 2021-06-14 @2402  int ad9545_probe(struct device *dev, struct regmap *regmap)
f88d17c990b731 Alexandru Tachici 2021-06-14  2403  {
f88d17c990b731 Alexandru Tachici 2021-06-14  2404  	struct ad9545_state *st;
f88d17c990b731 Alexandru Tachici 2021-06-14  2405  	int ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  2406  
f88d17c990b731 Alexandru Tachici 2021-06-14  2407  	st = devm_kzalloc(dev, sizeof(struct ad9545_state), GFP_KERNEL);
f88d17c990b731 Alexandru Tachici 2021-06-14  2408  	if (!st)
f88d17c990b731 Alexandru Tachici 2021-06-14  2409  		return -ENOMEM;
f88d17c990b731 Alexandru Tachici 2021-06-14  2410  
f88d17c990b731 Alexandru Tachici 2021-06-14  2411  	st->dev = dev;
f88d17c990b731 Alexandru Tachici 2021-06-14  2412  	st->regmap = regmap;
f88d17c990b731 Alexandru Tachici 2021-06-14  2413  
f88d17c990b731 Alexandru Tachici 2021-06-14  2414  	ret = ad9545_check_id(st);
f88d17c990b731 Alexandru Tachici 2021-06-14  2415  	if (ret < 0)
f88d17c990b731 Alexandru Tachici 2021-06-14  2416  		return ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  2417  
f88d17c990b731 Alexandru Tachici 2021-06-14  2418  	ret = ad9545_parse_dt(st);
f88d17c990b731 Alexandru Tachici 2021-06-14  2419  	if (ret < 0)
f88d17c990b731 Alexandru Tachici 2021-06-14  2420  		return ret;
f88d17c990b731 Alexandru Tachici 2021-06-14  2421  
f88d17c990b731 Alexandru Tachici 2021-06-14  2422  	return ad9545_setup(st);
f88d17c990b731 Alexandru Tachici 2021-06-14  2423  }
f88d17c990b731 Alexandru Tachici 2021-06-14  2424  EXPORT_SYMBOL_GPL(ad9545_probe);
f88d17c990b731 Alexandru Tachici 2021-06-14  2425  

---
0-DAY CI Kernel Test Service, Intel Corporation
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
diff mbox series

Patch

diff --git a/Documentation/devicetree/bindings/clock/clk-ad9545.yaml b/Documentation/devicetree/bindings/clock/clk-ad9545.yaml
new file mode 100644
index 000000000000..50553a88ab44
--- /dev/null
+++ b/Documentation/devicetree/bindings/clock/clk-ad9545.yaml
@@ -0,0 +1,556 @@ 
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/clk-ad9545.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Analog Devices AD9545 Quad Input, 10-Output, Dual DPLL/IEEE 1588
+
+maintainers:
+  - Alexandru Tachici <alexandru.tachici@analog.com>
+
+description: |
+  Analog Devices AD9545 Quad Input, 10-Output, Dual DPLL/IEEE 1588,
+  1 pps Synchronizer and Jitter Cleaner
+  https://www.analog.com/media/en/technical-documentation/data-sheets/ADM1266.pdf
+
+properties:
+  compatible:
+    enum:
+      - adi,ad9545
+
+  "#clock-cells":
+    const: 2
+
+  reg:
+    description: |
+      I2C address of the secondary device.
+    minimum: 0
+    maximum: 0xFF
+
+  avcc-supply:
+    description: |
+      Phandle to the Avcc power supply.
+
+  adi,freq-doubler:
+    description: |
+      The system clock PLL provides the user with the option of doubling the reference frequency.
+    type: boolean
+
+  adi,ref-crystal:
+    description: |
+      At XOA,XOB there is a crystal connected that needs maintaining.
+      Otherwise it is assumed that there is a TCXO or OCXO connected.
+    type: boolean
+
+  adi,ref-frequency-hz:
+    description: |
+      Reference input frequency at XOA,XOB. This is used for the system clock.
+
+  clocks:
+    items:
+      - description: Ref A clock input
+      - description: Ref AA clock input
+      - description: Ref B clock input
+      - description: Ref BB clock input
+      - description: Ref M0 clock input
+      - description: Ref M1 clock input
+      - description: Ref M2 clock input
+    maxItems: 4
+
+  assigned-clocks:
+    description:
+      Clocks are identified using two cells <&ad9545 clock_type clock_address>.
+    minItems: 1
+    maxItems: 14
+
+  assigned-clock-rates:
+    minItems: 1
+    maxItems: 14
+
+  assigned-clock-phases:
+    minItems: 1
+    maxItems: 14
+
+  clock-output-names:
+    maxItems: 10
+
+  aux-dpll:
+    description: |
+      Auxiliary DPLL used for Closed-Loop method of system clock compensation.
+    type: object
+
+    properties:
+      adi,compensation-source:
+        description: |
+          System clock closed loop compensation source.
+          Choose from Ref-A to Ref-BB [0-3] or aux TDCs [4-5].
+        $ref: /schemas/types.yaml#/definitions/uint32
+        enum: [0, 1, 2, 3, 4, 5]
+
+      adi,aux-dpll-bw-mhz:
+        description: |
+          Auxiliary DPLL bandwidth.
+        minimum: 100
+        maximum: 2000000
+
+      adi,rate-change-limit:
+        description: |
+          Error compensation rate change limiting expressed in ppb/s. Disabled if property is
+          missing.
+        $ref: /schemas/types.yaml#/definitions/uint32
+        enum: [715, 1430, 2860, 5720, 11440, 22880, 45760]
+
+    required:
+      - adi,compensation-source
+      - adi,aux-dpll-bw-mhz
+
+  aux-tdc-clks:
+    description: |
+      Child nodes represent Mx pin reference clock inputs.
+    type: object
+
+    properties:
+      '#address-cells':
+         const: 1
+
+      '#size-cells':
+         const: 0
+
+    patternProperties:
+      "^aux-tdc-clk@[0-3]$":
+
+        description: |
+          Represents a Mx pin reference clock input.
+        type: object
+
+        properties:
+          reg:
+            description: |
+              Address of the Auxiliary TDC.
+            maximum: 1
+
+          adi,pin-nr:
+            description: |
+              Pin number to be the source of this TDC.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 0
+            maximum: 6
+
+        required:
+          - reg
+          - adi,pin-nr
+
+    additionalProperties: false
+
+  ref-input-clks:
+    description: |
+      Child nodes represent reference clock inputs.
+    type: object
+
+    properties:
+      '#address-cells':
+         const: 1
+
+      '#size-cells':
+         const: 0
+
+    patternProperties:
+      "^ref-input-clk@[0-3]$":
+        description: |
+          Represents a reference clock input.
+        type: object
+
+        properties:
+          reg:
+            description: |
+              The reference input number. It can have up to 4 input clocks numbered from 0 to 3.
+              (mapped: [refa, refaa, refb, refbb] -> [0, 1, 2, 3])
+            maxItems: 1
+
+          adi,single-ended-mode:
+            description: |
+              Single-ended configuration mode.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            enum: [0, 1, 2, 3]
+
+          adi,differential-mode:
+            description: |
+              Differential configuration mode.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            enum: [0, 1, 2]
+
+          adi,r-divider-ratio:
+            description: |
+              Each reference input has a dedicated divider.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 1
+            maximum: 1073741824
+
+          adi,ref-dtol-pbb:
+            description: |
+              REFx offset limit. Constitutes a fractional portion of the corresponding nominal period.
+              The 24-bit number represents fractional units of parts per billion (ppb) up to a
+              maximum of approximately 17 million ppb (1.7%).
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 0
+            maximum: 16777215
+            default: 100000
+
+          adi,ref-monitor-hysteresis-pbb:
+            description: |
+              Basis points of the offset limit representing per ten thousand of REFx offset limit.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            enum: [0, 3125, 6250, 12500, 25000, 50000, 75000, 87500]
+            default: 12500
+
+          adi,ref-validation-timer-ms:
+            description: |
+              Time required for a reference to remain in tolerance condition before being
+              available to be used.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 1
+            maximum: 1048574
+            default: 10
+
+          adi,freq-lock-threshold-ps:
+            description: |
+              Phase lock detector threshold (in picoseconds).
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 1
+            maximum: 16777215
+
+          adi,phase-lock-threshold-ps:
+            description: |
+              Profile 0 frequency lock threshold. Frequency lock detector threshold (in picoseconds).
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 1
+            maximum: 16777215
+
+          adi,phase-lock-fill-rate:
+            description: |
+              Parameter used by the DPLL Phase Lock Detector.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 1
+            maximum: 255
+            default: 10
+
+          adi,phase-lock-drain-rate:
+            description: |
+              Parameter used by the DPLL Phase Lock Detector.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 1
+            maximum: 255
+            default: 10
+
+          adi,freq-lock-fill-rate:
+            description: |
+              Parameter used by the DPLL Frequency Lock Detector.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 1
+            maximum: 255
+            default: 10
+
+          adi,freq-lock-drain-rate:
+            description: |
+              Parameter used by the DPLL Frequency Lock Detector.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 1
+            maximum: 255
+            default: 10
+
+        required:
+          - reg
+          - adi,r-divider-ratio
+          - adi,ref-dtol-pbb
+          - adi,ref-monitor-hysteresis-pbb
+          - adi,ref-validation-timer-ms
+          - adi,freq-lock-threshold-ps
+          - adi,phase-lock-threshold-ps
+
+    additionalProperties: false
+
+  pll-clks:
+    description: |
+      Child nodes represent PLLs.
+    type: object
+
+    properties:
+      '#address-cells':
+         const: 1
+
+      '#size-cells':
+         const: 0
+
+    patternProperties:
+      "^pll-clk@[0-1]$":
+        description: |
+          Represents a PLL.
+        type: object
+
+        properties:
+          reg:
+            description: |
+              PLL number. AD9545 has two PLLs.
+            maxItems: 1
+
+          '#address-cells':
+             const: 1
+
+          '#size-cells':
+             const: 0
+
+          adi,fast-acq-trigger-mode:
+            description: |
+              If this is not specified Fast Acquisition will be used every time. See reg 0x2106
+              for constraints on Fast Acquisition trigger.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 0
+            maximum: 15
+            default: 0
+
+        patternProperties:
+          "^profile@[0-5]$":
+            description: |
+              Represents a DPLL profile. Each DPLL can have up to 6 specified sources
+              wih priorities assigned.
+            type: object
+
+            properties:
+              reg:
+                description: |
+                  Profile number. A DPLL can have up to 6 translation profiles.
+                maxItems: 1
+              adi,profile-priority:
+                description: |
+                  Profile selection priority. 0 is the highest, 31 is the lowest. For revertive
+                  reference switching, ensure that priority difference is > 7.
+                $ref: /schemas/types.yaml#/definitions/uint32
+                minimum: 0
+                maximum: 31
+
+              adi,pll-source:
+                description: |
+                  Each PLL can have 1 signal source. Choose from Ref-A to Ref-BB [0-3] or aux NCOs [4-5].
+                $ref: /schemas/types.yaml#/definitions/uint32
+                enum: [0, 1, 2, 3, 4, 5]
+
+              adi,pll-loop-bandwidth-uhz:
+                description: |
+                  PLL loop bandwidth in microhertz.
+                $ref: /schemas/types.yaml#/definitions/uint32
+                minimum: 1
+                maximum: 1850000000
+                default: 200000000
+
+              adi,fast-acq-excess-bw:
+                description: |
+                  Controls the DPLL loop bandwidth scaling factor while in fast acquisition mode.
+                  0 means this feature is disabled.
+                $ref: /schemas/types.yaml#/definitions/uint32
+                enum: [0, 2, 4, 8, 16, 32, 64, 128, 256, 512, 1024]
+                default: 0
+
+              adi,fast-acq-timeout-ms:
+                description: |
+                  Fast acquisition timeout controls the maximum amount of time that DPLL waits to
+                  achieve phase lock before reducing the loop bandwidth by a factor of two.
+                $ref: /schemas/types.yaml#/definitions/uint32
+                enum: [1, 10, 50, 100, 500, 1000, 10000, 50000]
+                default: 1
+
+              adi,fast-acq-lock-settle-ms:
+                description: |
+                  Controls how long DPLL must wait after achieving phase lock before reducing
+                  the loop bandwidth by a factor of 2.
+                $ref: /schemas/types.yaml#/definitions/uint32
+                enum: [1, 10, 50, 100, 500, 1000, 10000, 50000]
+                default: 1
+
+            required:
+              - reg
+              - adi,pll-source
+              - adi,pll-loop-bandwidth-uhz
+
+        additionalProperties: false
+
+        required:
+          - reg
+
+    additionalProperties: false
+
+  aux-ncos:
+    description: |
+      Child nodes represent auxiliary Numerical Controlled Oscilators.
+    type: object
+
+    properties:
+      '#address-cells':
+         const: 1
+
+      '#size-cells':
+         const: 0
+
+    patternProperties:
+      "^aux-nco-clk@[0-1]$":
+        description: |
+          Represents an auxiliary Numerical Controlled Oscilator. Generates timestamps that
+          can be sent to the DPLL0 or DPLL1.
+        type: object
+
+        properties:
+          reg:
+            description: |
+              Auxiliary NCO address mapped: [NCO0, NCO1] -> [0, 1].
+            maxItems: 1
+
+          adi,freq-lock-threshold-ps:
+            description: |
+              Phase lock detector threshold (in picoseconds).
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 1
+            maximum: 16777215
+
+          adi,phase-lock-threshold-ps:
+            description: |
+              Profile 0 frequency lock threshold. Frequency lock detector threshold (in picoseconds).
+            $ref: /schemas/types.yaml#/definitions/uint32
+            minimum: 1
+            maximum: 16777215
+
+        required:
+          - reg
+          - adi,freq-lock-threshold-ps
+          - adi,phase-lock-threshold-ps
+
+    additionalProperties: false
+
+  output-clks:
+    description: |
+      Child nodes represent clock outputs.
+    type: object
+
+    properties:
+      '#address-cells':
+         const: 1
+
+      '#size-cells':
+         const: 0
+
+    patternProperties:
+      "^output-clk@([0-9]|1[0-3])$":
+        description: |
+          Represents a clock output.
+        type: object
+
+        properties:
+          reg:
+            description: |
+              The reference input number. It can have up to 10 output clocks mapped:
+              (OUT0AP OUT0AN OUT0BP OUT0BN OUT0CP OUT0CN OUT1AP OUT1AN OUT1BP OUT1BN) ->
+              (0, 1, 2, 3, 4, 5, 6, 7, 8, 9)
+            maxItems: 1
+
+          adi,current-source:
+            description: |
+              If specified output is set as current source.
+            type: boolean
+
+          adi,current-source-microamp:
+            description: |
+              The magnitude of the driver current.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            enum: [7500, 12500, 15000]
+
+          adi,output-mode:
+            description: |
+              Output driver mode.
+            $ref: /schemas/types.yaml#/definitions/uint32
+            enum: [0, 1, 2]
+
+        required:
+          - reg
+          - adi,current-source-microamp
+          - adi,output-mode
+
+    additionalProperties: false
+
+required:
+  - compatible
+  - reg
+  - adi,ref-frequency-hz
+
+additionalProperties: false
+
+examples:
+  - |
+    #include <dt-bindings/clock/ad9545.h>
+
+    i2c1 {
+        #address-cells = <1>;
+        #size-cells = <0>;
+
+        ad9545_clock: ad9545@4A {
+                compatible = "adi,ad9545";
+                reg = <0x4A>;
+
+                adi,ref-crystal;
+                adi,ref-frequency-hz = <52000000>;
+
+                #clock-cells = <2>;
+                assigned-clocks = <&ad9545_clock AD9545_CLK_NCO AD9545_NCO0>,
+                                  <&ad9545_clock AD9545_CLK_PLL AD9545_PLL1>,
+                                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1A>,
+                                  <&ad9545_clock AD9545_CLK_OUT AD9545_Q1B>;
+                assigned-clock-rates = <10000>, <1875000000>, <156250000>, <156250000>;
+                assigned-clock-phases = <0>, <0>, <0>, <180>;
+
+                aux-ncos {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        aux-nco-clk@AD9545_NCO0 {
+                                reg = <AD9545_NCO0>;
+                                adi,freq-lock-threshold-ps = <16000000>;
+                                adi,phase-lock-threshold-ps = <16000000>;
+                        };
+                };
+
+                pll-clks {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        ad9545_apll1: pll-clk@AD9545_PLL1 {
+                                reg = <AD9545_PLL1>;
+
+                                #address-cells = <1>;
+                                #size-cells = <0>;
+
+                                profile@0 {
+                                       reg = <0>;
+                                       adi,pll-source = <4>;
+                                       adi,profile-priority = <0>;
+                                       adi,pll-loop-bandwidth-uhz = <200000000>;
+                                };
+                        };
+                };
+
+                output-clks {
+                        #address-cells = <1>;
+                        #size-cells = <0>;
+
+                        output-clk@AD9545_Q1A {
+                                reg = <AD9545_Q1A>;
+                                adi,output-mode = <DRIVER_MODE_DUAL_DIV>;
+                                adi,current-source-microamp = <15000>;
+                        };
+
+                        output-clk@AD9545_Q1B {
+                                reg = <AD9545_Q1B>;
+                                adi,output-mode = <DRIVER_MODE_DUAL_DIV>;
+                                adi,current-source-microamp = <15000>;
+                        };
+                };
+        };
+    };
+...
diff --git a/include/dt-bindings/clock/ad9545.h b/include/dt-bindings/clock/ad9545.h
new file mode 100644
index 000000000000..857d50e5715b
--- /dev/null
+++ b/include/dt-bindings/clock/ad9545.h
@@ -0,0 +1,69 @@ 
+/* SPDX-License-Identifier: GPL-2.0 OR BSD-2-Clause */
+/*
+ * AD9545 Network Clock Generator/Synchronizer
+ *
+ * Copyright 2020 Analog Devices Inc.
+ */
+
+#ifndef _DT_BINDINGS_CLOCK_AD9545_H_
+#define _DT_BINDINGS_CLOCK_AD9545_H_
+
+/* Input Driver Mode
+ * Use for adi,single-ended-mode:
+ */
+#define DRIVER_MODE_AC_COUPLED_IF	0
+#define DRIVER_MODE_DC_COUPLED_1V2	1
+#define DRIVER_MODE_DC_COUPLED_1V8	2
+#define DRIVER_MODE_IN_PULL_UP		3
+
+/* Input Driver Mode
+ * Use for adi,differential-mode:
+ */
+#define DRIVER_MODE_AC_COUPLED		0
+#define DRIVER_MODE_DC_COUPLED		1
+#define DRIVER_MODE_DC_COUPLED_LVDS	2
+
+/* Output Driver Mode
+ * Use for adi,output-mode:
+ */
+#define DRIVER_MODE_SINGLE_DIV_DIF	0
+#define DRIVER_MODE_SINGLE_DIV		1
+#define DRIVER_MODE_DUAL_DIV		2
+
+/* Clock types */
+#define AD9545_CLK_OUT			0
+#define AD9545_CLK_PLL			1
+#define AD9545_CLK_NCO			2
+#define AD9545_CLK_AUX_TDC		3
+
+/* PLL addresses */
+#define AD9545_PLL0			0
+#define AD9545_PLL1			1
+
+/* Outputs addresses */
+#define AD9545_Q0A			0
+#define AD9545_Q0AA			1
+#define AD9545_Q0B			2
+#define AD9545_Q0BB			3
+#define AD9545_Q0C			4
+#define AD9545_Q0CC			5
+#define AD9545_Q1A			6
+#define AD9545_Q1AA			7
+#define AD9545_Q1B			8
+#define AD9545_Q1BB			9
+
+/* NCO addresses */
+#define AD9545_NCO0			0
+#define AD9545_NCO1			1
+
+/* TDC addresses */
+#define AD9545_CLK_AUX_TDC0		0
+#define AD9545_CLK_AUX_TDC1		1
+
+/* Ex:
+ * Output Q0C clock: <&ad9545_clock AD9545_CLK_OUT AD9545_Q0C>;
+ * PLL0 clock: <&ad9545_clock AD9545_CLK_PLL AD9545_PLL0>;
+ * NCO1 clock: <&ad9545_clock AD9545_CLK_NCO AD9545_NCO1>;
+ */
+
+#endif /* _DT_BINDINGS_CLOCK_AD9545_H_ */