| Message ID | 20210514024845.10531-3-billy_tsai@aspeedtech.com |
|---|---|
| State | Superseded, archived |
| Headers | show |
| Series | Support pwm driver for aspeed ast26xx | expand |
Hello, On Fri, May 14, 2021 at 10:48:45AM +0800, Billy Tsai wrote: > This patch add the support of PWM controller which can be found at aspeed > ast2600 soc. The pwm supoorts up to 16 channels and it's part function > of multi-function device "pwm-tach controller". > > Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> > --- > drivers/pwm/Kconfig | 8 + > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-aspeed-g6.c | 355 ++++++++++++++++++++++++++++++++++++ > 3 files changed, 364 insertions(+) > create mode 100644 drivers/pwm/pwm-aspeed-g6.c > > diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig > index 63be5362fd3a..b0964b9a3273 100644 > --- a/drivers/pwm/Kconfig > +++ b/drivers/pwm/Kconfig > @@ -51,6 +51,14 @@ config PWM_AB8500 > To compile this driver as a module, choose M here: the module > will be called pwm-ab8500. > > +config PWM_ASPEED_G6 > + tristate "ASPEEDG6 PWM support" > + depends on ARCH_ASPEED || COMPILE_TEST > + help > + Generic PWM framework driver for ASPEED G6 SoC. > + > + This driver provides support for ASPEED G6 PWM controllers. The first sentence has little information, just the second is good enough, maybe mention the module name as the other driver items do. > + > config PWM_ATMEL > tristate "Atmel PWM support" > depends on OF > diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile > index cbdcd55d69ee..29d22d806e68 100644 > --- a/drivers/pwm/Makefile > +++ b/drivers/pwm/Makefile > @@ -2,6 +2,7 @@ > obj-$(CONFIG_PWM) += core.o > obj-$(CONFIG_PWM_SYSFS) += sysfs.o > obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o > +obj-$(CONFIG_PWM_ASPEED_G6) += pwm-aspeed-g6.o > obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o > obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o > obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o > diff --git a/drivers/pwm/pwm-aspeed-g6.c b/drivers/pwm/pwm-aspeed-g6.c > new file mode 100644 > index 000000000000..a3d0ad324a13 > --- /dev/null > +++ b/drivers/pwm/pwm-aspeed-g6.c > @@ -0,0 +1,355 @@ > +// SPDX-License-Identifier: GPL-2.0-or-later > +/* > + * Copyright (C) 2021 ASPEED Technology Inc. > + * > + * PWM controller driver for Aspeed ast26xx SoCs. > + * This drivers doesn't support earlier version of the IP. > + * > + * The formula of pwm frequency: > + * PWM frequency = CLK Source / ((DIV_L + 1) * BIT(DIV_H) * (PERIOD + 1)) > + * > + * The software driver fixes the period to 255, which causes the high-frequency > + * precision of the PWM to be coarse, in exchange for the fineness of the duty cycle. > + * > + * Register usage: > + * PIN_ENABLE: When it is unset the pwm controller will always output low to the extern. > + * Use to determine whether the PWM channel is enabled or disabled > + * CLK_ENABLE: When it is unset the pwm controller will reset the duty counter to 0 and > + * output low to the PIN_ENABLE mux after that the driver can still change the pwm period > + * and duty and the value will apply when CLK_ENABLE be set again. > + * Use to determin whether duty_cycle bigger than 0. > + * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately. > + * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two > + * values are equal it means the duty cycle = 100%. > + * > + * Limitations: > + * - When changing both duty cycle and period, we cannot prevent in > + * software that the output might produce a period with mixed > + * settings. > + * > + * Improvements: > + * - When changing the duty cycle or period, our pwm controller will not > + * generate the glitch, the configure will change at next cycle of pwm. > + * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE. > + */ > + > +#include <linux/clk.h> > +#include <linux/errno.h> > +#include <linux/delay.h> > +#include <linux/io.h> > +#include <linux/kernel.h> > +#include <linux/mfd/syscon.h> > +#include <linux/module.h> > +#include <linux/of_platform.h> > +#include <linux/of_device.h> > +#include <linux/platform_device.h> > +#include <linux/sysfs.h> > +#include <linux/reset.h> > +#include <linux/regmap.h> > +#include <linux/bitfield.h> > +#include <linux/slab.h> > +#include <linux/pwm.h> > + > +/* The channel number of Aspeed pwm controller */ > +#define PWM_ASPEED_NR_PWMS 16 > + > +/* PWM Control Register */ > +#define PWM_ASPEED_CTRL_CH(ch) ((((ch)*0x10) + 0x00)) The outer parenthesis pair can be dropped. > +#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19) > +#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18) > +#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17) > +#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16) > +#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15) > +#define PWM_ASPEED_CTRL_INVERSE BIT(14) > +#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13) > +#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12) > +#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8) > +#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0) > + > +/* PWM Duty Cycle Register */ > +#define PWM_ASPEED_DUTY_CYCLE_CH(ch) ((((ch)*0x10) + 0x04)) > +#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24) > +#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16) > +#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8) > +#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0) > + > +/* PWM fixed value */ > +#define PWM_ASPEED_FIXED_PERIOD 0xff > + > +struct aspeed_pwm_data { > + struct pwm_chip chip; > + struct clk *clk; > + struct regmap *regmap; > + struct reset_control *reset; > +}; > + > +static inline struct aspeed_pwm_data * > +aspeed_pwm_chip_to_data(struct pwm_chip *c) > +{ > + return container_of(c, struct aspeed_pwm_data, chip); > +} > + > +static u64 aspeed_pwm_get_period(struct pwm_chip *chip, struct pwm_device *pwm) > +{ > + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip); > + unsigned long rate; > + u32 index = pwm->hwpwm; > + u32 div_h, div_l, val; > + u64 period; > + > + rate = clk_get_rate(priv->clk); > + regmap_read(priv->regmap, PWM_ASPEED_CTRL_CH(index), &val); > + div_h = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_H, val); > + div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val); > + period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, rate); > + period *= (BIT(div_h) * (div_l + 1) * (PWM_ASPEED_FIXED_PERIOD + 1)); As this function is used in .get_state it makes sense to use the PWM_ASPEED_DUTY_CYCLE_PERIOD register value instead of PWM_ASPEED_FIXED_PERIOD in case the bootloader programmed doesn't implement the "always use 255" strategy. DIV_ROUND_UP_ULL doens't give any advantage here over plain DIV_ROUND_UP because both parameters fit into a plain unsigned long. However first doing the multiplication and only then the division increases precision. (Consider rate = 199000000, div_h = 2, div_l = 130 and PWM_ASPEED_DUTY_CYCLE_PERIOD = 255: The exact period is 674090.4522613066 ns. With your ordering you calculate 804864.0 ns, while when dividing at the end you get 674091.) > + > + return period; > +} > + > +static int aspeed_pwm_set_freq(struct pwm_chip *chip, struct pwm_device *pwm, > + const struct pwm_state *state) It's a bit irritating that this is called ..._set_freq but it is about the period. Maybe better call it ..._set_period? > +{ > + struct device *dev = chip->dev; > + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip); > + unsigned long rate; > + u64 div_h, div_l; > + u32 index = pwm->hwpwm; > + > + rate = clk_get_rate(priv->clk); > + rate = DIV_ROUND_UP_ULL(rate, (PWM_ASPEED_FIXED_PERIOD + 1)); You don't need parenthesis around the parameters of DIV_ROUND_UP_ULL. As you round up here, you don't necessarily calculate the smallest value for div_h, do you? > + /* Get the smallest value for div_h */ > + div_h = rate * state->period; Same issue as above, if you divide at the end of the calculation the precision is better. > + div_h = DIV_ROUND_DOWN_ULL(div_h, > + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1)); > + div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC); As a division is an expensive operation you can better first multiply NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 and divide by the result. > + > + div_h = order_base_2(div_h); > + if (div_h > 0xf) > + div_h = 0xf; > + > + div_l = rate * state->period; > + div_l >>= div_h; > + div_l = DIV_ROUND_DOWN_ULL(div_l, NSEC_PER_SEC); > + if (div_l == 0) { > + dev_err(dev, "Period too small, cannot implement it"); No error message please. > + return -ERANGE; > + } > + > + div_l -= 1; > + > + if (div_l > 255) > + div_l = 255; > + > + dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", rate, div_h, > + div_l); > + > + regmap_update_bits( > + priv->regmap, PWM_ASPEED_CTRL_CH(index), > + (PWM_ASPEED_CTRL_CLK_DIV_H | PWM_ASPEED_CTRL_CLK_DIV_L), > + FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) | > + FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l)); > + return 0; > +} > + > +static void aspeed_set_pwm_duty(struct pwm_chip *chip, struct pwm_device *pwm, > + const struct pwm_state *state) aspeed_pwm_set_duty please > +{ > + struct device *dev = chip->dev; > + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip); > + u32 duty_pt; > + u32 index = pwm->hwpwm; > + u64 cur_period; > + > + cur_period = aspeed_pwm_get_period(chip, pwm); > + duty_pt = DIV_ROUND_DOWN_ULL( > + state->duty_cycle * (PWM_ASPEED_FIXED_PERIOD + 1), cur_period); > + dev_dbg(dev, "cur_period = %lld, duty_cycle = %lld, duty_pt = %d\n", > + cur_period, state->duty_cycle, duty_pt); > + if (duty_pt == 0) { > + regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL_CH(index), > + PWM_ASPEED_CTRL_CLK_ENABLE, 0); > + } else { > + if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1)) > + duty_pt = 0; > + regmap_update_bits( > + priv->regmap, PWM_ASPEED_DUTY_CYCLE_CH(index), > + PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, > + FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, > + duty_pt)); > + regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL_CH(index), > + PWM_ASPEED_CTRL_CLK_ENABLE, > + PWM_ASPEED_CTRL_CLK_ENABLE); > + } > +} > + > +static void aspeed_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, > + struct pwm_state *state) > +{ > + struct device *dev = chip->dev; > + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip); > + u32 index = pwm->hwpwm; > + bool polarity, ch_en, clk_en; > + u32 duty_pt, val; > + > + regmap_read(priv->regmap, PWM_ASPEED_CTRL_CH(index), &val); > + polarity = FIELD_GET(PWM_ASPEED_CTRL_INVERSE, val); > + ch_en = FIELD_GET(PWM_ASPEED_CTRL_PIN_ENABLE, val); > + clk_en = FIELD_GET(PWM_ASPEED_CTRL_CLK_ENABLE, val); > + regmap_read(priv->regmap, PWM_ASPEED_DUTY_CYCLE_CH(index), &val); > + duty_pt = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, val); > + > + state->period = aspeed_pwm_get_period(chip, pwm); > + if (clk_en && duty_pt) > + state->duty_cycle = DIV_ROUND_DOWN_ULL( > + state->period * duty_pt, PWM_ASPEED_FIXED_PERIOD + 1); Round up please. > + else > + state->duty_cycle = clk_en ? state->period : 0; > + state->polarity = polarity; > + state->enabled = ch_en; > + dev_dbg(dev, "get period: %lldns, duty_cycle: %lldns", state->period, > + state->duty_cycle); > +} > + > +static int aspeed_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, > + const struct pwm_state *state) > +{ > + struct device *dev = chip->dev; > + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip); > + u32 index = pwm->hwpwm; > + int ret; > + > + dev_dbg(dev, "apply period: %lldns, duty_cycle: %lldns", state->period, > + state->duty_cycle); > + > + regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL_CH(index), > + PWM_ASPEED_CTRL_PIN_ENABLE, > + state->enabled ? PWM_ASPEED_CTRL_PIN_ENABLE : 0); > + /* > + * Fixed the period to the max value and rising point to 0 > + * for high resolution and simplify frequency calculation. > + */ > + regmap_update_bits(priv->regmap, PWM_ASPEED_DUTY_CYCLE_CH(index), > + (PWM_ASPEED_DUTY_CYCLE_PERIOD | > + PWM_ASPEED_DUTY_CYCLE_RISING_POINT), > + FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD, > + PWM_ASPEED_FIXED_PERIOD)); > + > + ret = aspeed_pwm_set_freq(chip, pwm, state); > + if (ret) > + return ret; > + aspeed_set_pwm_duty(chip, pwm, state); > + regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL_CH(index), > + PWM_ASPEED_CTRL_INVERSE, > + FIELD_PREP(PWM_ASPEED_CTRL_INVERSE, > + state->polarity)); > + return 0; > +} > + > +static const struct pwm_ops aspeed_pwm_ops = { > + .apply = aspeed_pwm_apply, > + .get_state = aspeed_pwm_get_state, > + .owner = THIS_MODULE, > +}; > + > +static int aspeed_pwm_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + int ret; > + struct aspeed_pwm_data *priv; > + struct device_node *np; > + struct platform_device *parent_dev; > + > + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); > + if (!priv) > + return -ENOMEM; > + > + np = pdev->dev.parent->of_node; > + if (!of_device_is_compatible(np, "aspeed,ast2600-pwm-tach")) { > + dev_err(dev, "unsupported pwm device binding\n"); > + return -ENODEV; You can simplify this to return dev_err_probe(dev, -ENODEV, "uns..."); > + } > + > + priv->regmap = syscon_node_to_regmap(np); > + if (IS_ERR(priv->regmap)) { > + return dev_err_probe(dev, PTR_ERR(priv->regmap), > + "Couldn't get regmap\n"); > + } No { } please > + > + parent_dev = of_find_device_by_node(np); > + priv->clk = devm_clk_get(&parent_dev->dev, 0); > + if (IS_ERR(priv->clk)) > + return dev_err_probe(dev, PTR_ERR(priv->clk), > + "get clock failed\n"); > + > + ret = clk_prepare_enable(priv->clk); > + if (ret) { > + dev_err(dev, "couldn't enable clock\n"); > + return ret; If you use dev_err_probe here this is more compact and the error message contains the error code. > + } > + > + priv->reset = of_reset_control_get_shared(np, NULL); > + if (IS_ERR(priv->reset)) > + return dev_err_probe(dev, PTR_ERR(priv->reset), > + "get reset failed\n"); > + > + ret = reset_control_deassert(priv->reset); > + if (ret) { > + dev_err(dev, "cannot deassert reset control: %pe\n", > + ERR_PTR(ret)); Best regards Uwe
Hello, On 2021/5/15, 11:57 PM,Uwe Kleine-Königwrote: > > + div_h = DIV_ROUND_DOWN_ULL(div_h, > > + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1)); > > + div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC); > As a division is an expensive operation you can better first multiply > NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 and divide by > the result. When I multiply NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 the result will overflow for 32-bits and the divisor type of do_div is 32-bits so I need to do div twice to avoid the issue. Can you give me some suggests? Thanks
Hello Billy, On Mon, May 17, 2021 at 02:53:44AM +0000, Billy Tsai wrote: > On 2021/5/15, 11:57 PM,Uwe Kleine-Königwrote: > > > > + div_h = DIV_ROUND_DOWN_ULL(div_h, > > > + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1)); > > > + div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC); > > > As a division is an expensive operation you can better first multiply > > NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 and divide by > > the result. > > When I multiply NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 the result will overflow > for 32-bits and the divisor type of do_div is 32-bits so I need to do div twice to avoid the issue. > Can you give me some suggests? Hmm, you're right. There doesn't seem to be a div64_64, I thought there was one. Anyhow, while looking at the various divide functions I saw that dividing by a constant shouldn't be that expensive, so I think the sane way is to keep the two divisions and add a comment describing the problem. Best regards Uwe
Hi, On 2021/5/17, 2:06 PM,Uwe Kleine-Königwrote: On Mon, May 17, 2021 at 02:53:44AM +0000, Billy Tsai wrote: > > On 2021/5/15, 11:57 PM,Uwe Kleine-Königwrote: > > > > > > + div_h = DIV_ROUND_DOWN_ULL(div_h, > > > > + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1)); > > > > + div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC); > > > > > As a division is an expensive operation you can better first multiply > > > NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 and divide by > > > the result. > > > > When I multiply NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 the result will overflow > > for 32-bits and the divisor type of do_div is 32-bits so I need to do div twice to avoid the issue. > > Can you give me some suggests? > Hmm, you're right. There doesn't seem to be a div64_64, I thought there > was one. Anyhow, while looking at the various divide functions I saw > that dividing by a constant shouldn't be that expensive, so I think the > sane way is to keep the two divisions and add a comment describing the > problem. According to our fixed value, I think that I can use bit shift to reduce one divide function: rate = clk_get_rate(priv->clk); /* Get the smallest value for div_h */ div_h = rate * state->period; div_h >>= (__fls(PWM_ASPEED_FIXED_PERIOD + 1) + __fls(FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1)); div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC); div_h = order_base_2(div_h); if (div_h > 0xf) div_h = 0xf; div_l = rate * state->period; div_l >>= (__fls(PWM_ASPEED_FIXED_PERIOD + 1) + div_h); div_l = DIV_ROUND_DOWN_ULL(div_l, NSEC_PER_SEC); How about this change of the driver? Thanks
On Mon, May 17, 2021 at 06:23:06AM +0000, Billy Tsai wrote: > Hi, > On 2021/5/17, 2:06 PM,Uwe Kleine-Königwrote: > > On Mon, May 17, 2021 at 02:53:44AM +0000, Billy Tsai wrote: > > > On 2021/5/15, 11:57 PM,Uwe Kleine-Königwrote: > > > > > > > > + div_h = DIV_ROUND_DOWN_ULL(div_h, > > > > > + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1)); > > > > > + div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC); > > > > > > > As a division is an expensive operation you can better first multiply > > > > NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 and divide by > > > > the result. > > > > > > When I multiply NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 the result will overflow > > > for 32-bits and the divisor type of do_div is 32-bits so I need to do div twice to avoid the issue. > > > Can you give me some suggests? > > > Hmm, you're right. There doesn't seem to be a div64_64, I thought there > > was one. Anyhow, while looking at the various divide functions I saw > > that dividing by a constant shouldn't be that expensive, so I think the > > sane way is to keep the two divisions and add a comment describing the > > problem. > According to our fixed value, I think that I can use bit shift to reduce one divide function: > > rate = clk_get_rate(priv->clk); > /* Get the smallest value for div_h */ > div_h = rate * state->period; > div_h >>= (__fls(PWM_ASPEED_FIXED_PERIOD + 1) + > __fls(FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1)); > div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC); Did you check how this is compiled to code? I'd expect that it doesn't result in better code than writing it as a division. Given that a division is easier to understand for a human reader, I'd stick to that. Best regards Uwe
Hi, > On 2021/5/17, 2:35 PM,Uwe Kleine-Königwrote: > On Mon, May 17, 2021 at 06:23:06AM +0000, Billy Tsai wrote: > > Hi, > > On 2021/5/17, 2:06 PM,Uwe Kleine-Königwrote: > > > > On Mon, May 17, 2021 at 02:53:44AM +0000, Billy Tsai wrote: > > > > On 2021/5/15, 11:57 PM,Uwe Kleine-Königwrote: > > > > > > > > > > + div_h = DIV_ROUND_DOWN_ULL(div_h, > > > > > > + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1)); > > > > > > + div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC); > > > > > > > > > As a division is an expensive operation you can better first multiply > > > > > NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 and divide by > > > > > the result. > > > > > > > > When I multiply NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 the result will overflow > > > > for 32-bits and the divisor type of do_div is 32-bits so I need to do div twice to avoid the issue. > > > > Can you give me some suggests? > > > > > Hmm, you're right. There doesn't seem to be a div64_64, I thought there > > > was one. Anyhow, while looking at the various divide functions I saw > > > that dividing by a constant shouldn't be that expensive, so I think the > > > sane way is to keep the two divisions and add a comment describing the > > > problem. > > According to our fixed value, I think that I can use bit shift to reduce one divide function: > > > > rate = clk_get_rate(priv->clk); > > /* Get the smallest value for div_h */ > > div_h = rate * state->period; > > div_h >>= (__fls(PWM_ASPEED_FIXED_PERIOD + 1) + > > __fls(FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1)); > > div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC); > Did you check how this is compiled to code? I'd expect that it doesn't > result in better code than writing it as a division. Given that a > division is easier to understand for a human reader, I'd stick to that. I found that I can use div64_64 through #include <linux/math64.h> and use "div64_u64": u64 div_h, div_l, divisor; u32 index = pwm->hwpwm; rate = clk_get_rate(priv->clk); /* Get the smallest value for div_h */ div_h = rate * state->period; divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) * (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1); div_h = div64_u64(div_h, divisor); div_h = order_base_2(div_h); if (div_h > 0xf) div_h = 0xf; div_l = rate * state->period; divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) * BIT(div_h); div_l = div64_u64(div_l, divisor); Can I use this one? Thanks
On Mon, May 17, 2021 at 07:12:53AM +0000, Billy Tsai wrote: > Hi, > > > On 2021/5/17, 2:35 PM,Uwe Kleine-Königwrote: > > > On Mon, May 17, 2021 at 06:23:06AM +0000, Billy Tsai wrote: > > > Hi, > > > On 2021/5/17, 2:06 PM,Uwe Kleine-Königwrote: > > > > > > On Mon, May 17, 2021 at 02:53:44AM +0000, Billy Tsai wrote: > > > > > On 2021/5/15, 11:57 PM,Uwe Kleine-Königwrote: > > > > > > > > > > > > + div_h = DIV_ROUND_DOWN_ULL(div_h, > > > > > > > + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1)); > > > > > > > + div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC); > > > > > > > > > > > As a division is an expensive operation you can better first multiply > > > > > > NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 and divide by > > > > > > the result. > > > > > > > > > > When I multiply NSEC_PER_SEC and FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1 the result will overflow > > > > > for 32-bits and the divisor type of do_div is 32-bits so I need to do div twice to avoid the issue. > > > > > Can you give me some suggests? > > > > > > > Hmm, you're right. There doesn't seem to be a div64_64, I thought there > > > > was one. Anyhow, while looking at the various divide functions I saw > > > > that dividing by a constant shouldn't be that expensive, so I think the > > > > sane way is to keep the two divisions and add a comment describing the > > > > problem. > > > According to our fixed value, I think that I can use bit shift to reduce one divide function: > > > > > > rate = clk_get_rate(priv->clk); > > > /* Get the smallest value for div_h */ > > > div_h = rate * state->period; > > > div_h >>= (__fls(PWM_ASPEED_FIXED_PERIOD + 1) + > > > __fls(FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1)); > > > div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC); > > > Did you check how this is compiled to code? I'd expect that it doesn't > > result in better code than writing it as a division. Given that a > > division is easier to understand for a human reader, I'd stick to that. > > I found that I can use div64_64 through #include <linux/math64.h> and use "div64_u64": > > u64 div_h, div_l, divisor; > u32 index = pwm->hwpwm; > > rate = clk_get_rate(priv->clk); > /* Get the smallest value for div_h */ > div_h = rate * state->period; > divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) * > (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1); > div_h = div64_u64(div_h, divisor); > div_h = order_base_2(div_h); > if (div_h > 0xf) > div_h = 0xf; > > div_l = rate * state->period; > divisor = (u64)NSEC_PER_SEC * (PWM_ASPEED_FIXED_PERIOD + 1) * > BIT(div_h); > div_l = div64_u64(div_l, divisor); > > Can I use this one? Looks good to me. If you want to improve further you can expand the comment about div_h to somethink like: /* * Pick a small value for div_h so that div_l can be big which * results in a finer resolution near the target period value. */ Another detail I don't like much is that the name div_h is only justified after the last assignment. I don't have a good suggestion here though. Best regards Uwe
diff --git a/drivers/pwm/Kconfig b/drivers/pwm/Kconfig index 63be5362fd3a..b0964b9a3273 100644 --- a/drivers/pwm/Kconfig +++ b/drivers/pwm/Kconfig @@ -51,6 +51,14 @@ config PWM_AB8500 To compile this driver as a module, choose M here: the module will be called pwm-ab8500. +config PWM_ASPEED_G6 + tristate "ASPEEDG6 PWM support" + depends on ARCH_ASPEED || COMPILE_TEST + help + Generic PWM framework driver for ASPEED G6 SoC. + + This driver provides support for ASPEED G6 PWM controllers. + config PWM_ATMEL tristate "Atmel PWM support" depends on OF diff --git a/drivers/pwm/Makefile b/drivers/pwm/Makefile index cbdcd55d69ee..29d22d806e68 100644 --- a/drivers/pwm/Makefile +++ b/drivers/pwm/Makefile @@ -2,6 +2,7 @@ obj-$(CONFIG_PWM) += core.o obj-$(CONFIG_PWM_SYSFS) += sysfs.o obj-$(CONFIG_PWM_AB8500) += pwm-ab8500.o +obj-$(CONFIG_PWM_ASPEED_G6) += pwm-aspeed-g6.o obj-$(CONFIG_PWM_ATMEL) += pwm-atmel.o obj-$(CONFIG_PWM_ATMEL_HLCDC_PWM) += pwm-atmel-hlcdc.o obj-$(CONFIG_PWM_ATMEL_TCB) += pwm-atmel-tcb.o diff --git a/drivers/pwm/pwm-aspeed-g6.c b/drivers/pwm/pwm-aspeed-g6.c new file mode 100644 index 000000000000..a3d0ad324a13 --- /dev/null +++ b/drivers/pwm/pwm-aspeed-g6.c @@ -0,0 +1,355 @@ +// SPDX-License-Identifier: GPL-2.0-or-later +/* + * Copyright (C) 2021 ASPEED Technology Inc. + * + * PWM controller driver for Aspeed ast26xx SoCs. + * This drivers doesn't support earlier version of the IP. + * + * The formula of pwm frequency: + * PWM frequency = CLK Source / ((DIV_L + 1) * BIT(DIV_H) * (PERIOD + 1)) + * + * The software driver fixes the period to 255, which causes the high-frequency + * precision of the PWM to be coarse, in exchange for the fineness of the duty cycle. + * + * Register usage: + * PIN_ENABLE: When it is unset the pwm controller will always output low to the extern. + * Use to determine whether the PWM channel is enabled or disabled + * CLK_ENABLE: When it is unset the pwm controller will reset the duty counter to 0 and + * output low to the PIN_ENABLE mux after that the driver can still change the pwm period + * and duty and the value will apply when CLK_ENABLE be set again. + * Use to determin whether duty_cycle bigger than 0. + * PWM_ASPEED_CTRL_INVERSE: When it is toggled the output value will inverse immediately. + * PWM_ASPEED_DUTY_CYCLE_FALLING_POINT/PWM_ASPEED_DUTY_CYCLE_RISING_POINT: When these two + * values are equal it means the duty cycle = 100%. + * + * Limitations: + * - When changing both duty cycle and period, we cannot prevent in + * software that the output might produce a period with mixed + * settings. + * + * Improvements: + * - When changing the duty cycle or period, our pwm controller will not + * generate the glitch, the configure will change at next cycle of pwm. + * This improvement can disable/enable through PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE. + */ + +#include <linux/clk.h> +#include <linux/errno.h> +#include <linux/delay.h> +#include <linux/io.h> +#include <linux/kernel.h> +#include <linux/mfd/syscon.h> +#include <linux/module.h> +#include <linux/of_platform.h> +#include <linux/of_device.h> +#include <linux/platform_device.h> +#include <linux/sysfs.h> +#include <linux/reset.h> +#include <linux/regmap.h> +#include <linux/bitfield.h> +#include <linux/slab.h> +#include <linux/pwm.h> + +/* The channel number of Aspeed pwm controller */ +#define PWM_ASPEED_NR_PWMS 16 + +/* PWM Control Register */ +#define PWM_ASPEED_CTRL_CH(ch) ((((ch)*0x10) + 0x00)) +#define PWM_ASPEED_CTRL_LOAD_SEL_RISING_AS_WDT BIT(19) +#define PWM_ASPEED_CTRL_DUTY_LOAD_AS_WDT_ENABLE BIT(18) +#define PWM_ASPEED_CTRL_DUTY_SYNC_DISABLE BIT(17) +#define PWM_ASPEED_CTRL_CLK_ENABLE BIT(16) +#define PWM_ASPEED_CTRL_LEVEL_OUTPUT BIT(15) +#define PWM_ASPEED_CTRL_INVERSE BIT(14) +#define PWM_ASPEED_CTRL_OPEN_DRAIN_ENABLE BIT(13) +#define PWM_ASPEED_CTRL_PIN_ENABLE BIT(12) +#define PWM_ASPEED_CTRL_CLK_DIV_H GENMASK(11, 8) +#define PWM_ASPEED_CTRL_CLK_DIV_L GENMASK(7, 0) + +/* PWM Duty Cycle Register */ +#define PWM_ASPEED_DUTY_CYCLE_CH(ch) ((((ch)*0x10) + 0x04)) +#define PWM_ASPEED_DUTY_CYCLE_PERIOD GENMASK(31, 24) +#define PWM_ASPEED_DUTY_CYCLE_POINT_AS_WDT GENMASK(23, 16) +#define PWM_ASPEED_DUTY_CYCLE_FALLING_POINT GENMASK(15, 8) +#define PWM_ASPEED_DUTY_CYCLE_RISING_POINT GENMASK(7, 0) + +/* PWM fixed value */ +#define PWM_ASPEED_FIXED_PERIOD 0xff + +struct aspeed_pwm_data { + struct pwm_chip chip; + struct clk *clk; + struct regmap *regmap; + struct reset_control *reset; +}; + +static inline struct aspeed_pwm_data * +aspeed_pwm_chip_to_data(struct pwm_chip *c) +{ + return container_of(c, struct aspeed_pwm_data, chip); +} + +static u64 aspeed_pwm_get_period(struct pwm_chip *chip, struct pwm_device *pwm) +{ + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip); + unsigned long rate; + u32 index = pwm->hwpwm; + u32 div_h, div_l, val; + u64 period; + + rate = clk_get_rate(priv->clk); + regmap_read(priv->regmap, PWM_ASPEED_CTRL_CH(index), &val); + div_h = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_H, val); + div_l = FIELD_GET(PWM_ASPEED_CTRL_CLK_DIV_L, val); + period = DIV_ROUND_UP_ULL(NSEC_PER_SEC, rate); + period *= (BIT(div_h) * (div_l + 1) * (PWM_ASPEED_FIXED_PERIOD + 1)); + + return period; +} + +static int aspeed_pwm_set_freq(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct device *dev = chip->dev; + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip); + unsigned long rate; + u64 div_h, div_l; + u32 index = pwm->hwpwm; + + rate = clk_get_rate(priv->clk); + rate = DIV_ROUND_UP_ULL(rate, (PWM_ASPEED_FIXED_PERIOD + 1)); + /* Get the smallest value for div_h */ + div_h = rate * state->period; + div_h = DIV_ROUND_DOWN_ULL(div_h, + (FIELD_MAX(PWM_ASPEED_CTRL_CLK_DIV_L) + 1)); + div_h = DIV_ROUND_DOWN_ULL(div_h, NSEC_PER_SEC); + + div_h = order_base_2(div_h); + if (div_h > 0xf) + div_h = 0xf; + + div_l = rate * state->period; + div_l >>= div_h; + div_l = DIV_ROUND_DOWN_ULL(div_l, NSEC_PER_SEC); + if (div_l == 0) { + dev_err(dev, "Period too small, cannot implement it"); + return -ERANGE; + } + + div_l -= 1; + + if (div_l > 255) + div_l = 255; + + dev_dbg(dev, "clk source: %ld div_h %lld, div_l : %lld\n", rate, div_h, + div_l); + + regmap_update_bits( + priv->regmap, PWM_ASPEED_CTRL_CH(index), + (PWM_ASPEED_CTRL_CLK_DIV_H | PWM_ASPEED_CTRL_CLK_DIV_L), + FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_H, div_h) | + FIELD_PREP(PWM_ASPEED_CTRL_CLK_DIV_L, div_l)); + return 0; +} + +static void aspeed_set_pwm_duty(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct device *dev = chip->dev; + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip); + u32 duty_pt; + u32 index = pwm->hwpwm; + u64 cur_period; + + cur_period = aspeed_pwm_get_period(chip, pwm); + duty_pt = DIV_ROUND_DOWN_ULL( + state->duty_cycle * (PWM_ASPEED_FIXED_PERIOD + 1), cur_period); + dev_dbg(dev, "cur_period = %lld, duty_cycle = %lld, duty_pt = %d\n", + cur_period, state->duty_cycle, duty_pt); + if (duty_pt == 0) { + regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL_CH(index), + PWM_ASPEED_CTRL_CLK_ENABLE, 0); + } else { + if (duty_pt >= (PWM_ASPEED_FIXED_PERIOD + 1)) + duty_pt = 0; + regmap_update_bits( + priv->regmap, PWM_ASPEED_DUTY_CYCLE_CH(index), + PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, + FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, + duty_pt)); + regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL_CH(index), + PWM_ASPEED_CTRL_CLK_ENABLE, + PWM_ASPEED_CTRL_CLK_ENABLE); + } +} + +static void aspeed_pwm_get_state(struct pwm_chip *chip, struct pwm_device *pwm, + struct pwm_state *state) +{ + struct device *dev = chip->dev; + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip); + u32 index = pwm->hwpwm; + bool polarity, ch_en, clk_en; + u32 duty_pt, val; + + regmap_read(priv->regmap, PWM_ASPEED_CTRL_CH(index), &val); + polarity = FIELD_GET(PWM_ASPEED_CTRL_INVERSE, val); + ch_en = FIELD_GET(PWM_ASPEED_CTRL_PIN_ENABLE, val); + clk_en = FIELD_GET(PWM_ASPEED_CTRL_CLK_ENABLE, val); + regmap_read(priv->regmap, PWM_ASPEED_DUTY_CYCLE_CH(index), &val); + duty_pt = FIELD_GET(PWM_ASPEED_DUTY_CYCLE_FALLING_POINT, val); + + state->period = aspeed_pwm_get_period(chip, pwm); + if (clk_en && duty_pt) + state->duty_cycle = DIV_ROUND_DOWN_ULL( + state->period * duty_pt, PWM_ASPEED_FIXED_PERIOD + 1); + else + state->duty_cycle = clk_en ? state->period : 0; + state->polarity = polarity; + state->enabled = ch_en; + dev_dbg(dev, "get period: %lldns, duty_cycle: %lldns", state->period, + state->duty_cycle); +} + +static int aspeed_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm, + const struct pwm_state *state) +{ + struct device *dev = chip->dev; + struct aspeed_pwm_data *priv = aspeed_pwm_chip_to_data(chip); + u32 index = pwm->hwpwm; + int ret; + + dev_dbg(dev, "apply period: %lldns, duty_cycle: %lldns", state->period, + state->duty_cycle); + + regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL_CH(index), + PWM_ASPEED_CTRL_PIN_ENABLE, + state->enabled ? PWM_ASPEED_CTRL_PIN_ENABLE : 0); + /* + * Fixed the period to the max value and rising point to 0 + * for high resolution and simplify frequency calculation. + */ + regmap_update_bits(priv->regmap, PWM_ASPEED_DUTY_CYCLE_CH(index), + (PWM_ASPEED_DUTY_CYCLE_PERIOD | + PWM_ASPEED_DUTY_CYCLE_RISING_POINT), + FIELD_PREP(PWM_ASPEED_DUTY_CYCLE_PERIOD, + PWM_ASPEED_FIXED_PERIOD)); + + ret = aspeed_pwm_set_freq(chip, pwm, state); + if (ret) + return ret; + aspeed_set_pwm_duty(chip, pwm, state); + regmap_update_bits(priv->regmap, PWM_ASPEED_CTRL_CH(index), + PWM_ASPEED_CTRL_INVERSE, + FIELD_PREP(PWM_ASPEED_CTRL_INVERSE, + state->polarity)); + return 0; +} + +static const struct pwm_ops aspeed_pwm_ops = { + .apply = aspeed_pwm_apply, + .get_state = aspeed_pwm_get_state, + .owner = THIS_MODULE, +}; + +static int aspeed_pwm_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + int ret; + struct aspeed_pwm_data *priv; + struct device_node *np; + struct platform_device *parent_dev; + + priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + np = pdev->dev.parent->of_node; + if (!of_device_is_compatible(np, "aspeed,ast2600-pwm-tach")) { + dev_err(dev, "unsupported pwm device binding\n"); + return -ENODEV; + } + + priv->regmap = syscon_node_to_regmap(np); + if (IS_ERR(priv->regmap)) { + return dev_err_probe(dev, PTR_ERR(priv->regmap), + "Couldn't get regmap\n"); + } + + parent_dev = of_find_device_by_node(np); + priv->clk = devm_clk_get(&parent_dev->dev, 0); + if (IS_ERR(priv->clk)) + return dev_err_probe(dev, PTR_ERR(priv->clk), + "get clock failed\n"); + + ret = clk_prepare_enable(priv->clk); + if (ret) { + dev_err(dev, "couldn't enable clock\n"); + return ret; + } + + priv->reset = of_reset_control_get_shared(np, NULL); + if (IS_ERR(priv->reset)) + return dev_err_probe(dev, PTR_ERR(priv->reset), + "get reset failed\n"); + + ret = reset_control_deassert(priv->reset); + if (ret) { + dev_err(dev, "cannot deassert reset control: %pe\n", + ERR_PTR(ret)); + goto err_disable_clk; + } + + priv->chip.dev = dev; + priv->chip.ops = &aspeed_pwm_ops; + priv->chip.npwm = PWM_ASPEED_NR_PWMS; + priv->chip.of_xlate = of_pwm_xlate_with_flags; + priv->chip.of_pwm_n_cells = 3; + + ret = pwmchip_add(&priv->chip); + if (ret < 0) { + dev_err(dev, "failed to add PWM chip: %pe\n", ERR_PTR(ret)); + goto err_assert_reset; + } + dev_set_drvdata(dev, priv); + return 0; +err_assert_reset: + reset_control_assert(priv->reset); +err_disable_clk: + clk_disable_unprepare(priv->clk); + return ret; +} + +static int aspeed_pwm_remove(struct platform_device *dev) +{ + struct aspeed_pwm_data *priv = platform_get_drvdata(dev); + + pwmchip_remove(&priv->chip); + reset_control_assert(priv->reset); + clk_disable_unprepare(priv->clk); + + return 0; +} + +static const struct of_device_id of_pwm_match_table[] = { + { + .compatible = "aspeed,ast2600-pwm", + }, + {}, +}; +MODULE_DEVICE_TABLE(of, of_pwm_match_table); + +static struct platform_driver aspeed_pwm_driver = { + .probe = aspeed_pwm_probe, + .remove = aspeed_pwm_remove, + .driver = { + .name = "aspeed_pwm", + .of_match_table = of_pwm_match_table, + }, +}; + +module_platform_driver(aspeed_pwm_driver); + +MODULE_AUTHOR("Billy Tsai <billy_tsai@aspeedtech.com>"); +MODULE_DESCRIPTION("ASPEED PWM device driver"); +MODULE_LICENSE("GPL v2");
This patch add the support of PWM controller which can be found at aspeed ast2600 soc. The pwm supoorts up to 16 channels and it's part function of multi-function device "pwm-tach controller". Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> --- drivers/pwm/Kconfig | 8 + drivers/pwm/Makefile | 1 + drivers/pwm/pwm-aspeed-g6.c | 355 ++++++++++++++++++++++++++++++++++++ 3 files changed, 364 insertions(+) create mode 100644 drivers/pwm/pwm-aspeed-g6.c