| Message ID | 20210430071302.1489082-5-bmeng.cn@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2,1/8] hw/riscv: sifive_u: Switch to use qemu_fdt_setprop_string_array() helper | expand |
On Fri, Apr 30, 2021 at 5:18 PM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > The supported device bullet list has an additional space before each > entry, which makes a wrong indentation level. Correct it. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > (no changes since v1) > > docs/system/riscv/microchip-icicle-kit.rst | 20 +++++++-------- > docs/system/riscv/sifive_u.rst | 30 +++++++++++----------- > 2 files changed, 25 insertions(+), 25 deletions(-) > > diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst > index 4fe97bce3f..e803131763 100644 > --- a/docs/system/riscv/microchip-icicle-kit.rst > +++ b/docs/system/riscv/microchip-icicle-kit.rst > @@ -15,16 +15,16 @@ Supported devices > > The ``microchip-icicle-kit`` machine supports the following devices: > > - * 1 E51 core > - * 4 U54 cores > - * Core Level Interruptor (CLINT) > - * Platform-Level Interrupt Controller (PLIC) > - * L2 Loosely Integrated Memory (L2-LIM) > - * DDR memory controller > - * 5 MMUARTs > - * 1 DMA controller > - * 2 GEM Ethernet controllers > - * 1 SDHC storage controller > +* 1 E51 core > +* 4 U54 cores > +* Core Level Interruptor (CLINT) > +* Platform-Level Interrupt Controller (PLIC) > +* L2 Loosely Integrated Memory (L2-LIM) > +* DDR memory controller > +* 5 MMUARTs > +* 1 DMA controller > +* 2 GEM Ethernet controllers > +* 1 SDHC storage controller > > Boot options > ------------ > diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst > index 98e7562848..dcdfbda931 100644 > --- a/docs/system/riscv/sifive_u.rst > +++ b/docs/system/riscv/sifive_u.rst > @@ -9,21 +9,21 @@ Supported devices > > The ``sifive_u`` machine supports the following devices: > > - * 1 E51 / E31 core > - * Up to 4 U54 / U34 cores > - * Core Level Interruptor (CLINT) > - * Platform-Level Interrupt Controller (PLIC) > - * Power, Reset, Clock, Interrupt (PRCI) > - * L2 Loosely Integrated Memory (L2-LIM) > - * DDR memory controller > - * 2 UARTs > - * 1 GEM Ethernet controller > - * 1 GPIO controller > - * 1 One-Time Programmable (OTP) memory with stored serial number > - * 1 DMA controller > - * 2 QSPI controllers > - * 1 ISSI 25WP256 flash > - * 1 SD card in SPI mode > +* 1 E51 / E31 core > +* Up to 4 U54 / U34 cores > +* Core Level Interruptor (CLINT) > +* Platform-Level Interrupt Controller (PLIC) > +* Power, Reset, Clock, Interrupt (PRCI) > +* L2 Loosely Integrated Memory (L2-LIM) > +* DDR memory controller > +* 2 UARTs > +* 1 GEM Ethernet controller > +* 1 GPIO controller > +* 1 One-Time Programmable (OTP) memory with stored serial number > +* 1 DMA controller > +* 2 QSPI controllers > +* 1 ISSI 25WP256 flash > +* 1 SD card in SPI mode > > Please note the real world HiFive Unleashed board has a fixed configuration of > 1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode. > -- > 2.25.1 > >
diff --git a/docs/system/riscv/microchip-icicle-kit.rst b/docs/system/riscv/microchip-icicle-kit.rst index 4fe97bce3f..e803131763 100644 --- a/docs/system/riscv/microchip-icicle-kit.rst +++ b/docs/system/riscv/microchip-icicle-kit.rst @@ -15,16 +15,16 @@ Supported devices The ``microchip-icicle-kit`` machine supports the following devices: - * 1 E51 core - * 4 U54 cores - * Core Level Interruptor (CLINT) - * Platform-Level Interrupt Controller (PLIC) - * L2 Loosely Integrated Memory (L2-LIM) - * DDR memory controller - * 5 MMUARTs - * 1 DMA controller - * 2 GEM Ethernet controllers - * 1 SDHC storage controller +* 1 E51 core +* 4 U54 cores +* Core Level Interruptor (CLINT) +* Platform-Level Interrupt Controller (PLIC) +* L2 Loosely Integrated Memory (L2-LIM) +* DDR memory controller +* 5 MMUARTs +* 1 DMA controller +* 2 GEM Ethernet controllers +* 1 SDHC storage controller Boot options ------------ diff --git a/docs/system/riscv/sifive_u.rst b/docs/system/riscv/sifive_u.rst index 98e7562848..dcdfbda931 100644 --- a/docs/system/riscv/sifive_u.rst +++ b/docs/system/riscv/sifive_u.rst @@ -9,21 +9,21 @@ Supported devices The ``sifive_u`` machine supports the following devices: - * 1 E51 / E31 core - * Up to 4 U54 / U34 cores - * Core Level Interruptor (CLINT) - * Platform-Level Interrupt Controller (PLIC) - * Power, Reset, Clock, Interrupt (PRCI) - * L2 Loosely Integrated Memory (L2-LIM) - * DDR memory controller - * 2 UARTs - * 1 GEM Ethernet controller - * 1 GPIO controller - * 1 One-Time Programmable (OTP) memory with stored serial number - * 1 DMA controller - * 2 QSPI controllers - * 1 ISSI 25WP256 flash - * 1 SD card in SPI mode +* 1 E51 / E31 core +* Up to 4 U54 / U34 cores +* Core Level Interruptor (CLINT) +* Platform-Level Interrupt Controller (PLIC) +* Power, Reset, Clock, Interrupt (PRCI) +* L2 Loosely Integrated Memory (L2-LIM) +* DDR memory controller +* 2 UARTs +* 1 GEM Ethernet controller +* 1 GPIO controller +* 1 One-Time Programmable (OTP) memory with stored serial number +* 1 DMA controller +* 2 QSPI controllers +* 1 ISSI 25WP256 flash +* 1 SD card in SPI mode Please note the real world HiFive Unleashed board has a fixed configuration of 1 E51 core and 4 U54 core combination and the RISC-V core boots in 64-bit mode.