[00/38] target/riscv: support packed extension v0.9.2

Message ID	20210212150256.885-1-zhiwei_liu@c-sky.com
Headers	show Return-Path: <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org> From: LIU Zhiwei <zhiwei_liu@c-sky.com> To: qemu-devel@nongnu.org Subject: [PATCH 00/38] target/riscv: support packed extension v0.9.2 Date: Fri, 12 Feb 2021 23:02:18 +0800 Message-Id: <20210212150256.885-1-zhiwei_liu@c-sky.com> Received-SPF: none client-ip=198.11.142.1; envelope-from=zhiwei_liu@c-sky.com; helo=mail142-1.mail.alibaba.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, RCVD_IN_DNSWL_LOW=-0.7, RCVD_IN_MSPIKE_H4=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_NONE=0.001, T_SPF_HELO_TEMPERROR=0.01, UNPARSEABLE_RELAY=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action Precedence: list Cc: richard.henderson@linaro.org, LIU Zhiwei <zhiwei_liu@c-sky.com>, qemu-riscv@nongnu.org, palmer@dabbelt.com, alistair23@gmail.com Errors-To: qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org Sender: "Qemu-devel" <qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org>
Series	target/riscv: support packed extension v0.9.2 \| expand [00/38] target/riscv: support packed extension v0.9.2 [01/38] target/riscv: implementation-defined constant parameters [02/38] target/riscv: Hoist vector functions [03/38] target/riscv: Fixup saturate subtract function [04/38] target/riscv: 16-bit Addition & Subtraction Instructions [05/38] target/riscv: 8-bit Addition & Subtraction Instruction [06/38] target/riscv: SIMD 16-bit Shift Instructions [07/38] target/riscv: SIMD 8-bit Shift Instructions [08/38] target/riscv: SIMD 16-bit Compare Instructions [09/38] target/riscv: SIMD 8-bit Compare Instructions [10/38] target/riscv: SIMD 16-bit Multiply Instructions [11/38] target/riscv: SIMD 8-bit Multiply Instructions [12/38] target/riscv: SIMD 16-bit Miscellaneous Instructions [13/38] target/riscv: SIMD 8-bit Miscellaneous Instructions [14/38] target/riscv: 8-bit Unpacking Instructions [15/38] target/riscv: 16-bit Packing Instructions [16/38] target/riscv: Signed MSW 32x32 Multiply and Add Instructions [17/38] target/riscv: Signed MSW 32x16 Multiply and Add Instructions [18/38] target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions [19/38] target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions [20/38] target/riscv: Partial-SIMD Miscellaneous Instructions [21/38] target/riscv: 8-bit Multiply with 32-bit Add Instructions [22/38] target/riscv: 64-bit Add/Subtract Instructions [23/38] target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions [24/38] target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract Instructions [25/38] target/riscv: Non-SIMD Q15 saturation ALU Instructions [26/38] target/riscv: Non-SIMD Q31 saturation ALU Instructions [27/38] target/riscv: 32-bit Computation Instructions [28/38] target/riscv: Non-SIMD Miscellaneous Instructions [29/38] target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions [30/38] target/riscv: RV64 Only SIMD 32-bit Shift Instructions [31/38] target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions [32/38] target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions [33/38] target/riscv: RV64 Only 32-bit Multiply Instructions [34/38] target/riscv: RV64 Only 32-bit Multiply & Add Instructions [35/38] target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions [36/38] target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions [37/38] target/riscv: RV64 Only 32-bit Packing Instructions [38/38] target/riscv: configure and turn on packed extension from command line

Message ID

20210212150256.885-1-zhiwei_liu@c-sky.com

Headers

From: LIU Zhiwei <zhiwei_liu@c-sky.com>
To: qemu-devel@nongnu.org
Subject: [PATCH 00/38] target/riscv: support packed extension v0.9.2
Date: Fri, 12 Feb 2021 23:02:18 +0800
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Series

target/riscv: support packed extension v0.9.2 | expand

Message

LIU Zhiwei Feb. 12, 2021, 3:02 p.m. UTC

This patchset implements the packed extension for RISC-V on QEMU.

This patchset have passed all my direct Linux user mode cases(RV64) and
bare metal cases(RV32) on X86-64 Ubuntu host machine. I will later push
these test cases to my repo(https://github.com/romanheros/qemu.git
branch:packed-upstream-v1).

I have ported packed extension on RISU, but I didn't find a simulator or
hardware to compare with. If anyone have one, please let me know.

Features:
  * support specification packed extension v0.9.2(https://github.com/riscv/riscv-p-spec/)
  * support basic packed extension.
  * support Zp64.

LIU Zhiwei (38):
  target/riscv: implementation-defined constant parameters
  target/riscv: Hoist vector functions
  target/riscv: Fixup saturate subtract function
  target/riscv: 16-bit Addition & Subtraction Instructions
  target/riscv: 8-bit Addition & Subtraction Instruction
  target/riscv: SIMD 16-bit Shift Instructions
  target/riscv: SIMD 8-bit Shift Instructions
  target/riscv: SIMD 16-bit Compare Instructions
  target/riscv: SIMD 8-bit Compare Instructions
  target/riscv: SIMD 16-bit Multiply Instructions
  target/riscv: SIMD 8-bit Multiply Instructions
  target/riscv: SIMD 16-bit Miscellaneous Instructions
  target/riscv: SIMD 8-bit Miscellaneous Instructions
  target/riscv: 8-bit Unpacking Instructions
  target/riscv: 16-bit Packing Instructions
  target/riscv: Signed MSW 32x32 Multiply and Add Instructions
  target/riscv: Signed MSW 32x16 Multiply and Add Instructions
  target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
  target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions
  target/riscv: Partial-SIMD Miscellaneous Instructions
  target/riscv: 8-bit Multiply with 32-bit Add Instructions
  target/riscv: 64-bit Add/Subtract Instructions
  target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions
  target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract
    Instructions
  target/riscv: Non-SIMD Q15 saturation ALU Instructions
  target/riscv: Non-SIMD Q31 saturation ALU Instructions
  target/riscv: 32-bit Computation Instructions
  target/riscv: Non-SIMD Miscellaneous Instructions
  target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
  target/riscv: RV64 Only SIMD 32-bit Shift Instructions
  target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
  target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
  target/riscv: RV64 Only 32-bit Multiply Instructions
  target/riscv: RV64 Only 32-bit Multiply & Add Instructions
  target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
  target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
  target/riscv: RV64 Only 32-bit Packing Instructions
  target/riscv: configure and turn on packed extension from command line

 target/riscv/cpu.c                      |   32 +
 target/riscv/cpu.h                      |    6 +
 target/riscv/helper.h                   |  332 ++
 target/riscv/insn32-64.decode           |   93 +-
 target/riscv/insn32.decode              |  285 ++
 target/riscv/insn_trans/trans_rvp.c.inc | 1224 +++++++
 target/riscv/internals.h                |   50 +
 target/riscv/meson.build                |    1 +
 target/riscv/packed_helper.c            | 3862 +++++++++++++++++++++++
 target/riscv/translate.c                |    3 +
 target/riscv/vector_helper.c            |   90 +-
 11 files changed, 5912 insertions(+), 66 deletions(-)
 create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc
 create mode 100644 target/riscv/packed_helper.c

Comments

LIU Zhiwei March 5, 2021, 6:14 a.m. UTC | #1

ping

On 2021/2/12 23:02, LIU Zhiwei wrote:
> This patchset implements the packed extension for RISC-V on QEMU.
>
> This patchset have passed all my direct Linux user mode cases(RV64) and
> bare metal cases(RV32) on X86-64 Ubuntu host machine. I will later push
> these test cases to my repo(https://github.com/romanheros/qemu.git
> branch:packed-upstream-v1).
>
> I have ported packed extension on RISU, but I didn't find a simulator or
> hardware to compare with. If anyone have one, please let me know.
>
> Features:
>    * support specification packed extension v0.9.2(https://github.com/riscv/riscv-p-spec/)
>    * support basic packed extension.
>    * support Zp64.
>
> LIU Zhiwei (38):
>    target/riscv: implementation-defined constant parameters
>    target/riscv: Hoist vector functions
>    target/riscv: Fixup saturate subtract function
>    target/riscv: 16-bit Addition & Subtraction Instructions
>    target/riscv: 8-bit Addition & Subtraction Instruction
>    target/riscv: SIMD 16-bit Shift Instructions
>    target/riscv: SIMD 8-bit Shift Instructions
>    target/riscv: SIMD 16-bit Compare Instructions
>    target/riscv: SIMD 8-bit Compare Instructions
>    target/riscv: SIMD 16-bit Multiply Instructions
>    target/riscv: SIMD 8-bit Multiply Instructions
>    target/riscv: SIMD 16-bit Miscellaneous Instructions
>    target/riscv: SIMD 8-bit Miscellaneous Instructions
>    target/riscv: 8-bit Unpacking Instructions
>    target/riscv: 16-bit Packing Instructions
>    target/riscv: Signed MSW 32x32 Multiply and Add Instructions
>    target/riscv: Signed MSW 32x16 Multiply and Add Instructions
>    target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
>    target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions
>    target/riscv: Partial-SIMD Miscellaneous Instructions
>    target/riscv: 8-bit Multiply with 32-bit Add Instructions
>    target/riscv: 64-bit Add/Subtract Instructions
>    target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions
>    target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract
>      Instructions
>    target/riscv: Non-SIMD Q15 saturation ALU Instructions
>    target/riscv: Non-SIMD Q31 saturation ALU Instructions
>    target/riscv: 32-bit Computation Instructions
>    target/riscv: Non-SIMD Miscellaneous Instructions
>    target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
>    target/riscv: RV64 Only SIMD 32-bit Shift Instructions
>    target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
>    target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
>    target/riscv: RV64 Only 32-bit Multiply Instructions
>    target/riscv: RV64 Only 32-bit Multiply & Add Instructions
>    target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
>    target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
>    target/riscv: RV64 Only 32-bit Packing Instructions
>    target/riscv: configure and turn on packed extension from command line
>
>   target/riscv/cpu.c                      |   32 +
>   target/riscv/cpu.h                      |    6 +
>   target/riscv/helper.h                   |  332 ++
>   target/riscv/insn32-64.decode           |   93 +-
>   target/riscv/insn32.decode              |  285 ++
>   target/riscv/insn_trans/trans_rvp.c.inc | 1224 +++++++
>   target/riscv/internals.h                |   50 +
>   target/riscv/meson.build                |    1 +
>   target/riscv/packed_helper.c            | 3862 +++++++++++++++++++++++
>   target/riscv/translate.c                |    3 +
>   target/riscv/vector_helper.c            |   90 +-
>   11 files changed, 5912 insertions(+), 66 deletions(-)
>   create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc
>   create mode 100644 target/riscv/packed_helper.c
>

LIU Zhiwei April 13, 2021, 3:27 a.m. UTC | #2

ping +1.

On 2021/2/12 下午11:02, LIU Zhiwei wrote:
> This patchset implements the packed extension for RISC-V on QEMU.
>
> This patchset have passed all my direct Linux user mode cases(RV64) and
> bare metal cases(RV32) on X86-64 Ubuntu host machine. I will later push
> these test cases to my repo(https://github.com/romanheros/qemu.git
> branch:packed-upstream-v1).
>
> I have ported packed extension on RISU, but I didn't find a simulator or
> hardware to compare with. If anyone have one, please let me know.
>
> Features:
>    * support specification packed extension v0.9.2(https://github.com/riscv/riscv-p-spec/)
>    * support basic packed extension.
>    * support Zp64.
>
> LIU Zhiwei (38):
>    target/riscv: implementation-defined constant parameters
>    target/riscv: Hoist vector functions
>    target/riscv: Fixup saturate subtract function
>    target/riscv: 16-bit Addition & Subtraction Instructions
>    target/riscv: 8-bit Addition & Subtraction Instruction
>    target/riscv: SIMD 16-bit Shift Instructions
>    target/riscv: SIMD 8-bit Shift Instructions
>    target/riscv: SIMD 16-bit Compare Instructions
>    target/riscv: SIMD 8-bit Compare Instructions
>    target/riscv: SIMD 16-bit Multiply Instructions
>    target/riscv: SIMD 8-bit Multiply Instructions
>    target/riscv: SIMD 16-bit Miscellaneous Instructions
>    target/riscv: SIMD 8-bit Miscellaneous Instructions
>    target/riscv: 8-bit Unpacking Instructions
>    target/riscv: 16-bit Packing Instructions
>    target/riscv: Signed MSW 32x32 Multiply and Add Instructions
>    target/riscv: Signed MSW 32x16 Multiply and Add Instructions
>    target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
>    target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions
>    target/riscv: Partial-SIMD Miscellaneous Instructions
>    target/riscv: 8-bit Multiply with 32-bit Add Instructions
>    target/riscv: 64-bit Add/Subtract Instructions
>    target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions
>    target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract
>      Instructions
>    target/riscv: Non-SIMD Q15 saturation ALU Instructions
>    target/riscv: Non-SIMD Q31 saturation ALU Instructions
>    target/riscv: 32-bit Computation Instructions
>    target/riscv: Non-SIMD Miscellaneous Instructions
>    target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
>    target/riscv: RV64 Only SIMD 32-bit Shift Instructions
>    target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
>    target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
>    target/riscv: RV64 Only 32-bit Multiply Instructions
>    target/riscv: RV64 Only 32-bit Multiply & Add Instructions
>    target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
>    target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
>    target/riscv: RV64 Only 32-bit Packing Instructions
>    target/riscv: configure and turn on packed extension from command line
>
>   target/riscv/cpu.c                      |   32 +
>   target/riscv/cpu.h                      |    6 +
>   target/riscv/helper.h                   |  332 ++
>   target/riscv/insn32-64.decode           |   93 +-
>   target/riscv/insn32.decode              |  285 ++
>   target/riscv/insn_trans/trans_rvp.c.inc | 1224 +++++++
>   target/riscv/internals.h                |   50 +
>   target/riscv/meson.build                |    1 +
>   target/riscv/packed_helper.c            | 3862 +++++++++++++++++++++++
>   target/riscv/translate.c                |    3 +
>   target/riscv/vector_helper.c            |   90 +-
>   11 files changed, 5912 insertions(+), 66 deletions(-)
>   create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc
>   create mode 100644 target/riscv/packed_helper.c
>

Alistair Francis April 15, 2021, 4:46 a.m. UTC | #3

On Tue, Apr 13, 2021 at 1:28 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>
> ping +1.
>
> On 2021/2/12 下午11:02, LIU Zhiwei wrote:
> > This patchset implements the packed extension for RISC-V on QEMU.
> >
> > This patchset have passed all my direct Linux user mode cases(RV64) and
> > bare metal cases(RV32) on X86-64 Ubuntu host machine. I will later push
> > these test cases to my repo(https://github.com/romanheros/qemu.git
> > branch:packed-upstream-v1).
> >
> > I have ported packed extension on RISU, but I didn't find a simulator or
> > hardware to compare with. If anyone have one, please let me know.
> >
> > Features:
> >    * support specification packed extension v0.9.2(https://github.com/riscv/riscv-p-spec/)
> >    * support basic packed extension.
> >    * support Zp64.
> >
> > LIU Zhiwei (38):
> >    target/riscv: implementation-defined constant parameters
> >    target/riscv: Hoist vector functions
> >    target/riscv: Fixup saturate subtract function

Thanks for the patches and sorry for the long delay.

I have applied patch 3 as it fixes a bug.

As for the other patches they are on both my review queue and Palmer's
review queue. It takes a lot of time to review these large patch
series, especially as I haven't been involved with the extension
development, so I have to both understand the extension and then
review the code.

If you would like to help speed things up you could review other
patches. That way I will have more time left to review your patches.

Alistair

> >    target/riscv: 16-bit Addition & Subtraction Instructions
> >    target/riscv: 8-bit Addition & Subtraction Instruction
> >    target/riscv: SIMD 16-bit Shift Instructions
> >    target/riscv: SIMD 8-bit Shift Instructions
> >    target/riscv: SIMD 16-bit Compare Instructions
> >    target/riscv: SIMD 8-bit Compare Instructions
> >    target/riscv: SIMD 16-bit Multiply Instructions
> >    target/riscv: SIMD 8-bit Multiply Instructions
> >    target/riscv: SIMD 16-bit Miscellaneous Instructions
> >    target/riscv: SIMD 8-bit Miscellaneous Instructions
> >    target/riscv: 8-bit Unpacking Instructions
> >    target/riscv: 16-bit Packing Instructions
> >    target/riscv: Signed MSW 32x32 Multiply and Add Instructions
> >    target/riscv: Signed MSW 32x16 Multiply and Add Instructions
> >    target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
> >    target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions
> >    target/riscv: Partial-SIMD Miscellaneous Instructions
> >    target/riscv: 8-bit Multiply with 32-bit Add Instructions
> >    target/riscv: 64-bit Add/Subtract Instructions
> >    target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions
> >    target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract
> >      Instructions
> >    target/riscv: Non-SIMD Q15 saturation ALU Instructions
> >    target/riscv: Non-SIMD Q31 saturation ALU Instructions
> >    target/riscv: 32-bit Computation Instructions
> >    target/riscv: Non-SIMD Miscellaneous Instructions
> >    target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
> >    target/riscv: RV64 Only SIMD 32-bit Shift Instructions
> >    target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
> >    target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
> >    target/riscv: RV64 Only 32-bit Multiply Instructions
> >    target/riscv: RV64 Only 32-bit Multiply & Add Instructions
> >    target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
> >    target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
> >    target/riscv: RV64 Only 32-bit Packing Instructions
> >    target/riscv: configure and turn on packed extension from command line
> >
> >   target/riscv/cpu.c                      |   32 +
> >   target/riscv/cpu.h                      |    6 +
> >   target/riscv/helper.h                   |  332 ++
> >   target/riscv/insn32-64.decode           |   93 +-
> >   target/riscv/insn32.decode              |  285 ++
> >   target/riscv/insn_trans/trans_rvp.c.inc | 1224 +++++++
> >   target/riscv/internals.h                |   50 +
> >   target/riscv/meson.build                |    1 +
> >   target/riscv/packed_helper.c            | 3862 +++++++++++++++++++++++
> >   target/riscv/translate.c                |    3 +
> >   target/riscv/vector_helper.c            |   90 +-
> >   11 files changed, 5912 insertions(+), 66 deletions(-)
> >   create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc
> >   create mode 100644 target/riscv/packed_helper.c
> >

LIU Zhiwei April 15, 2021, 5:50 a.m. UTC | #4

On 2021/4/15 下午12:46, Alistair Francis wrote:
> On Tue, Apr 13, 2021 at 1:28 PM LIU Zhiwei <zhiwei_liu@c-sky.com> wrote:
>> ping +1.
>>
>> On 2021/2/12 下午11:02, LIU Zhiwei wrote:
>>> This patchset implements the packed extension for RISC-V on QEMU.
>>>
>>> This patchset have passed all my direct Linux user mode cases(RV64) and
>>> bare metal cases(RV32) on X86-64 Ubuntu host machine. I will later push
>>> these test cases to my repo(https://github.com/romanheros/qemu.git
>>> branch:packed-upstream-v1).
>>>
>>> I have ported packed extension on RISU, but I didn't find a simulator or
>>> hardware to compare with. If anyone have one, please let me know.
>>>
>>> Features:
>>>     * support specification packed extension v0.9.2(https://github.com/riscv/riscv-p-spec/)
>>>     * support basic packed extension.
>>>     * support Zp64.
>>>
>>> LIU Zhiwei (38):
>>>     target/riscv: implementation-defined constant parameters
>>>     target/riscv: Hoist vector functions
>>>     target/riscv: Fixup saturate subtract function
> Thanks for the patches and sorry for the long delay.
>
> I have applied patch 3 as it fixes a bug.
> As for the other patches they are on both my review queue and Palmer's
> review queue. It takes a lot of time to review these large patch
> series, especially as I haven't been involved with the extension
> development, so I have to both understand the extension and then
> review the code.
>
> If you would like to help speed things up you could review other
> patches. That way I will have more time left to review your patches.

No worries. I fully understand the great efforts needed to review so 
many patches. Firstly, I will try to review as many  as I send.

Zhiwei

> Alistair
>
>>>     target/riscv: 16-bit Addition & Subtraction Instructions
>>>     target/riscv: 8-bit Addition & Subtraction Instruction
>>>     target/riscv: SIMD 16-bit Shift Instructions
>>>     target/riscv: SIMD 8-bit Shift Instructions
>>>     target/riscv: SIMD 16-bit Compare Instructions
>>>     target/riscv: SIMD 8-bit Compare Instructions
>>>     target/riscv: SIMD 16-bit Multiply Instructions
>>>     target/riscv: SIMD 8-bit Multiply Instructions
>>>     target/riscv: SIMD 16-bit Miscellaneous Instructions
>>>     target/riscv: SIMD 8-bit Miscellaneous Instructions
>>>     target/riscv: 8-bit Unpacking Instructions
>>>     target/riscv: 16-bit Packing Instructions
>>>     target/riscv: Signed MSW 32x32 Multiply and Add Instructions
>>>     target/riscv: Signed MSW 32x16 Multiply and Add Instructions
>>>     target/riscv: Signed 16-bit Multiply 32-bit Add/Subtract Instructions
>>>     target/riscv: Signed 16-bit Multiply 64-bit Add/Subtract Instructions
>>>     target/riscv: Partial-SIMD Miscellaneous Instructions
>>>     target/riscv: 8-bit Multiply with 32-bit Add Instructions
>>>     target/riscv: 64-bit Add/Subtract Instructions
>>>     target/riscv: 32-bit Multiply 64-bit Add/Subtract Instructions
>>>     target/riscv: Signed 16-bit Multiply with 64-bit Add/Subtract
>>>       Instructions
>>>     target/riscv: Non-SIMD Q15 saturation ALU Instructions
>>>     target/riscv: Non-SIMD Q31 saturation ALU Instructions
>>>     target/riscv: 32-bit Computation Instructions
>>>     target/riscv: Non-SIMD Miscellaneous Instructions
>>>     target/riscv: RV64 Only SIMD 32-bit Add/Subtract Instructions
>>>     target/riscv: RV64 Only SIMD 32-bit Shift Instructions
>>>     target/riscv: RV64 Only SIMD 32-bit Miscellaneous Instructions
>>>     target/riscv: RV64 Only SIMD Q15 saturating Multiply Instructions
>>>     target/riscv: RV64 Only 32-bit Multiply Instructions
>>>     target/riscv: RV64 Only 32-bit Multiply & Add Instructions
>>>     target/riscv: RV64 Only 32-bit Parallel Multiply & Add Instructions
>>>     target/riscv: RV64 Only Non-SIMD 32-bit Shift Instructions
>>>     target/riscv: RV64 Only 32-bit Packing Instructions
>>>     target/riscv: configure and turn on packed extension from command line
>>>
>>>    target/riscv/cpu.c                      |   32 +
>>>    target/riscv/cpu.h                      |    6 +
>>>    target/riscv/helper.h                   |  332 ++
>>>    target/riscv/insn32-64.decode           |   93 +-
>>>    target/riscv/insn32.decode              |  285 ++
>>>    target/riscv/insn_trans/trans_rvp.c.inc | 1224 +++++++
>>>    target/riscv/internals.h                |   50 +
>>>    target/riscv/meson.build                |    1 +
>>>    target/riscv/packed_helper.c            | 3862 +++++++++++++++++++++++
>>>    target/riscv/translate.c                |    3 +
>>>    target/riscv/vector_helper.c            |   90 +-
>>>    11 files changed, 5912 insertions(+), 66 deletions(-)
>>>    create mode 100644 target/riscv/insn_trans/trans_rvp.c.inc
>>>    create mode 100644 target/riscv/packed_helper.c
>>>