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[0/2] A64/R40 DRAM controller dual-rank-related changes

Message ID 20210225161325.94019-1-icenowy@aosc.io
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Series A64/R40 DRAM controller dual-rank-related changes | expand

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Icenowy Zheng Feb. 25, 2021, 4:13 p.m. UTC 
This patchset contains two patches.

The first one enables asymmetric dual rank DRAM on A64. This is needed
for 3GiB PinePhone, which has 2GiB rank 0 and 1GiB rank 1. This patch is
already used by the firmware flashed to PinePhone by factory.

The second one enables dual rank (and asymmetric dual rank, although not
tested because of lack of real board) on R40. In order to support single
rank and dual rank at the same time, a new rank detection code is
implemented (because PIR_QSGATE-based one does not work on R40). The
code enables some error report facility of the DRAM controller, and
then tries to access rank 1 and then check for error. It's placed at 2nd
patch because it depends on the function that calculates rank 0 size
(and rank 1 base address) introduced in PATCH 1.

Icenowy Zheng (2):
  sunxi: support asymmetric dual rank DRAM on A64/R40
  sunxi: enable dual rank memory on R40

 .../include/asm/arch-sunxi/dram_sunxi_dw.h    |  11 +-
 arch/arm/mach-sunxi/dram_sunxi_dw.c           | 149 +++++++++++++++---
 2 files changed, 131 insertions(+), 29 deletions(-)

Comments

Andre Przywara March 31, 2021, 3:57 p.m. UTC | #1 
On Fri, 26 Feb 2021 00:13:23 +0800
Icenowy Zheng <icenowy@aosc.io> wrote:

> This patchset contains two patches.
> 
> The first one enables asymmetric dual rank DRAM on A64. This is needed
> for 3GiB PinePhone, which has 2GiB rank 0 and 1GiB rank 1. This patch is
> already used by the firmware flashed to PinePhone by factory.
> 
> The second one enables dual rank (and asymmetric dual rank, although not
> tested because of lack of real board) on R40. In order to support single
> rank and dual rank at the same time, a new rank detection code is
> implemented (because PIR_QSGATE-based one does not work on R40). The
> code enables some error report facility of the DRAM controller, and
> then tries to access rank 1 and then check for error. It's placed at 2nd
> patch because it depends on the function that calculates rank 0 size
> (and rank 1 base address) introduced in PATCH 1.

Thanks, queued both for -next.
I moved the call to mctl_r40_detect_rank_count() and mctl_set_cr() into
sunxi_dram_init(), to avoid the size regression.

Cheers,
Andre


> 
> Icenowy Zheng (2):
>   sunxi: support asymmetric dual rank DRAM on A64/R40
>   sunxi: enable dual rank memory on R40
> 
>  .../include/asm/arch-sunxi/dram_sunxi_dw.h    |  11 +-
>  arch/arm/mach-sunxi/dram_sunxi_dw.c           | 149 +++++++++++++++---
>  2 files changed, 131 insertions(+), 29 deletions(-)
>