diff mbox series

[v2,09/22] tcg/riscv: Split out target constraints to tcg-target-con-str.h

Message ID 20210115210456.1053477-10-richard.henderson@linaro.org
State New
Headers show
Series tcg: backend constraints cleanup | expand

Commit Message

Richard Henderson Jan. 15, 2021, 9:04 p.m. UTC 
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 tcg/riscv/tcg-target-con-str.h | 21 ++++++++++++++
 tcg/riscv/tcg-target.h         |  1 +
 tcg/riscv/tcg-target.c.inc     | 50 ++++++++--------------------------
 3 files changed, 33 insertions(+), 39 deletions(-)
 create mode 100644 tcg/riscv/tcg-target-con-str.h

Comments

Alistair Francis Jan. 15, 2021, 10:13 p.m. UTC | #1 
On Fri, Jan 15, 2021 at 1:09 PM Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  tcg/riscv/tcg-target-con-str.h | 21 ++++++++++++++
>  tcg/riscv/tcg-target.h         |  1 +
>  tcg/riscv/tcg-target.c.inc     | 50 ++++++++--------------------------
>  3 files changed, 33 insertions(+), 39 deletions(-)
>  create mode 100644 tcg/riscv/tcg-target-con-str.h
>
> diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
> new file mode 100644
> index 0000000000..587fcd3593
> --- /dev/null
> +++ b/tcg/riscv/tcg-target-con-str.h
> @@ -0,0 +1,21 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Define RISC-V target-specific operand constraints.
> + * Copyright (c) 2021 Linaro
> + */
> +
> +/*
> + * Define constraint letters for register sets:
> + * REGS(letter, register_mask)
> + */
> +REGS('r', ALL_GENERAL_REGS)
> +REGS('L', ALL_QLDST_REGS)
> +
> +/*
> + * Define constraint letters for constants:
> + * CONST(letter, TCG_CT_CONST_* bit set)
> + */
> +CONST('I', TCG_CT_CONST_S12)
> +CONST('N', TCG_CT_CONST_N12)
> +CONST('M', TCG_CT_CONST_M12)
> +CONST('Z', TCG_CT_CONST_ZERO)
> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
> index 727c8df418..daf3ef7b5c 100644
> --- a/tcg/riscv/tcg-target.h
> +++ b/tcg/riscv/tcg-target.h
> @@ -171,5 +171,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
>  #define TCG_TARGET_NEED_POOL_LABELS
>
>  #define TCG_TARGET_HAS_MEMORY_BSWAP 0
> +#define TCG_TARGET_CON_STR_H
>
>  #endif
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index 71c0badc02..185b569f4b 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -122,6 +122,17 @@ static const int tcg_target_call_oarg_regs[] = {
>  #define TCG_CT_CONST_N12   0x400
>  #define TCG_CT_CONST_M12   0x800
>
> +#define ALL_GENERAL_REGS  0xffffffffu
> +#ifdef CONFIG_SOFTMMU
> +#define ALL_QLDST_REGS \
> +    (ALL_GENERAL_REGS & ~((1 << TCG_REG_A0) | (1 << TCG_REG_A1) | \
> +                          (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | \
> +                          (1 << TCG_REG_A5)))

Why is this not TCG_REG_A4?

Alistair

> +#else
> +#define ALL_QLDST_REGS   ALL_GENERAL_REGS
> +#endif
> +
> +
>  static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
>  {
>      if (TCG_TARGET_REG_BITS == 32) {
> @@ -131,45 +142,6 @@ static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
>      }
>  }
>
> -/* parse target specific constraints */
> -static const char *target_parse_constraint(TCGArgConstraint *ct,
> -                                           const char *ct_str, TCGType type)
> -{
> -    switch (*ct_str++) {
> -    case 'r':
> -        ct->regs = 0xffffffff;
> -        break;
> -    case 'L':
> -        /* qemu_ld/qemu_st constraint */
> -        ct->regs = 0xffffffff;
> -        /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
> -#if defined(CONFIG_SOFTMMU)
> -        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
> -        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
> -        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
> -        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
> -        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
> -#endif
> -        break;
> -    case 'I':
> -        ct->ct |= TCG_CT_CONST_S12;
> -        break;
> -    case 'N':
> -        ct->ct |= TCG_CT_CONST_N12;
> -        break;
> -    case 'M':
> -        ct->ct |= TCG_CT_CONST_M12;
> -        break;
> -    case 'Z':
> -        /* we can use a zero immediate as a zero register argument. */
> -        ct->ct |= TCG_CT_CONST_ZERO;
> -        break;
> -    default:
> -        return NULL;
> -    }
> -    return ct_str;
> -}
> -
>  /* test if a constant matches the constraint */
>  static int tcg_target_const_match(tcg_target_long val, TCGType type,
>                                    const TCGArgConstraint *arg_ct)
> --
> 2.25.1
>
>
Richard Henderson Jan. 15, 2021, 10:39 p.m. UTC | #2 
On 1/15/21 12:13 PM, Alistair Francis wrote:
> On Fri, Jan 15, 2021 at 1:09 PM Richard Henderson
> <richard.henderson@linaro.org> wrote:
>>
>> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
>> ---
>>  tcg/riscv/tcg-target-con-str.h | 21 ++++++++++++++
>>  tcg/riscv/tcg-target.h         |  1 +
>>  tcg/riscv/tcg-target.c.inc     | 50 ++++++++--------------------------
>>  3 files changed, 33 insertions(+), 39 deletions(-)
>>  create mode 100644 tcg/riscv/tcg-target-con-str.h
>>
>> diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
>> new file mode 100644
>> index 0000000000..587fcd3593
>> --- /dev/null
>> +++ b/tcg/riscv/tcg-target-con-str.h
>> @@ -0,0 +1,21 @@
>> +/* SPDX-License-Identifier: MIT */
>> +/*
>> + * Define RISC-V target-specific operand constraints.
>> + * Copyright (c) 2021 Linaro
>> + */
>> +
>> +/*
>> + * Define constraint letters for register sets:
>> + * REGS(letter, register_mask)
>> + */
>> +REGS('r', ALL_GENERAL_REGS)
>> +REGS('L', ALL_QLDST_REGS)
>> +
>> +/*
>> + * Define constraint letters for constants:
>> + * CONST(letter, TCG_CT_CONST_* bit set)
>> + */
>> +CONST('I', TCG_CT_CONST_S12)
>> +CONST('N', TCG_CT_CONST_N12)
>> +CONST('M', TCG_CT_CONST_M12)
>> +CONST('Z', TCG_CT_CONST_ZERO)
>> diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
>> index 727c8df418..daf3ef7b5c 100644
>> --- a/tcg/riscv/tcg-target.h
>> +++ b/tcg/riscv/tcg-target.h
>> @@ -171,5 +171,6 @@ void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
>>  #define TCG_TARGET_NEED_POOL_LABELS
>>
>>  #define TCG_TARGET_HAS_MEMORY_BSWAP 0
>> +#define TCG_TARGET_CON_STR_H
>>
>>  #endif
>> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
>> index 71c0badc02..185b569f4b 100644
>> --- a/tcg/riscv/tcg-target.c.inc
>> +++ b/tcg/riscv/tcg-target.c.inc
>> @@ -122,6 +122,17 @@ static const int tcg_target_call_oarg_regs[] = {
>>  #define TCG_CT_CONST_N12   0x400
>>  #define TCG_CT_CONST_M12   0x800
>>
>> +#define ALL_GENERAL_REGS  0xffffffffu
>> +#ifdef CONFIG_SOFTMMU
>> +#define ALL_QLDST_REGS \
>> +    (ALL_GENERAL_REGS & ~((1 << TCG_REG_A0) | (1 << TCG_REG_A1) | \
>> +                          (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | \
>> +                          (1 << TCG_REG_A5)))
> 
> Why is this not TCG_REG_A4?

Typo, thanks.


r~
Peter Maydell Jan. 19, 2021, 2:52 p.m. UTC | #3 
On Fri, 15 Jan 2021 at 21:11, Richard Henderson
<richard.henderson@linaro.org> wrote:
>
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>  tcg/riscv/tcg-target-con-str.h | 21 ++++++++++++++
>  tcg/riscv/tcg-target.h         |  1 +
>  tcg/riscv/tcg-target.c.inc     | 50 ++++++++--------------------------
>  3 files changed, 33 insertions(+), 39 deletions(-)
>  create mode 100644 tcg/riscv/tcg-target-con-str.h
>
> +#define ALL_GENERAL_REGS  0xffffffffu
> +#ifdef CONFIG_SOFTMMU
> +#define ALL_QLDST_REGS \
> +    (ALL_GENERAL_REGS & ~((1 << TCG_REG_A0) | (1 << TCG_REG_A1) | \
> +                          (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | \
> +                          (1 << TCG_REG_A5)))
> +#else
> +#define ALL_QLDST_REGS   ALL_GENERAL_REGS
> +#endif

Other than the typo Alistair points out here,
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

thanks
-- PMM
Richard Henderson Jan. 19, 2021, 10:59 p.m. UTC | #4 
On 1/15/21 12:13 PM, Alistair Francis wrote:
>> +#define ALL_GENERAL_REGS  0xffffffffu
>> +#ifdef CONFIG_SOFTMMU
>> +#define ALL_QLDST_REGS \
>> +    (ALL_GENERAL_REGS & ~((1 << TCG_REG_A0) | (1 << TCG_REG_A1) | \
>> +                          (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | \
>> +                          (1 << TCG_REG_A5)))
> 
> Why is this not TCG_REG_A4?

I've changed this to

#define ALL_GENERAL_REGS      MAKE_64BIT_MASK(0, 32)
/*
 * For softmmu, we need to avoid conflicts with the first 5
 * argument registers to call the helper.  Some of these are
 * also used for the tlb lookup.
 */
#ifdef CONFIG_SOFTMMU
#define SOFTMMU_RESERVE_REGS  MAKE_64BIT_MASK(TCG_REG_A0, 5)
#else
#define SOFTMMU_RESERVE_REGS  0
#endif


r~
diff mbox series

Patch

diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
new file mode 100644
index 0000000000..587fcd3593
--- /dev/null
+++ b/tcg/riscv/tcg-target-con-str.h
@@ -0,0 +1,21 @@ 
+/* SPDX-License-Identifier: MIT */
+/*
+ * Define RISC-V target-specific operand constraints.
+ * Copyright (c) 2021 Linaro
+ */
+
+/*
+ * Define constraint letters for register sets:
+ * REGS(letter, register_mask)
+ */
+REGS('r', ALL_GENERAL_REGS)
+REGS('L', ALL_QLDST_REGS)
+
+/*
+ * Define constraint letters for constants:
+ * CONST(letter, TCG_CT_CONST_* bit set)
+ */
+CONST('I', TCG_CT_CONST_S12)
+CONST('N', TCG_CT_CONST_N12)
+CONST('M', TCG_CT_CONST_M12)
+CONST('Z', TCG_CT_CONST_ZERO)
diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h
index 727c8df418..daf3ef7b5c 100644
--- a/tcg/riscv/tcg-target.h
+++ b/tcg/riscv/tcg-target.h
@@ -171,5 +171,6 @@  void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t, uintptr_t);
 #define TCG_TARGET_NEED_POOL_LABELS
 
 #define TCG_TARGET_HAS_MEMORY_BSWAP 0
+#define TCG_TARGET_CON_STR_H
 
 #endif
diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
index 71c0badc02..185b569f4b 100644
--- a/tcg/riscv/tcg-target.c.inc
+++ b/tcg/riscv/tcg-target.c.inc
@@ -122,6 +122,17 @@  static const int tcg_target_call_oarg_regs[] = {
 #define TCG_CT_CONST_N12   0x400
 #define TCG_CT_CONST_M12   0x800
 
+#define ALL_GENERAL_REGS  0xffffffffu
+#ifdef CONFIG_SOFTMMU
+#define ALL_QLDST_REGS \
+    (ALL_GENERAL_REGS & ~((1 << TCG_REG_A0) | (1 << TCG_REG_A1) | \
+                          (1 << TCG_REG_A2) | (1 << TCG_REG_A3) | \
+                          (1 << TCG_REG_A5)))
+#else
+#define ALL_QLDST_REGS   ALL_GENERAL_REGS
+#endif
+
+
 static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
 {
     if (TCG_TARGET_REG_BITS == 32) {
@@ -131,45 +142,6 @@  static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len)
     }
 }
 
-/* parse target specific constraints */
-static const char *target_parse_constraint(TCGArgConstraint *ct,
-                                           const char *ct_str, TCGType type)
-{
-    switch (*ct_str++) {
-    case 'r':
-        ct->regs = 0xffffffff;
-        break;
-    case 'L':
-        /* qemu_ld/qemu_st constraint */
-        ct->regs = 0xffffffff;
-        /* qemu_ld/qemu_st uses TCG_REG_TMP0 */
-#if defined(CONFIG_SOFTMMU)
-        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[0]);
-        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[1]);
-        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[2]);
-        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[3]);
-        tcg_regset_reset_reg(ct->regs, tcg_target_call_iarg_regs[4]);
-#endif
-        break;
-    case 'I':
-        ct->ct |= TCG_CT_CONST_S12;
-        break;
-    case 'N':
-        ct->ct |= TCG_CT_CONST_N12;
-        break;
-    case 'M':
-        ct->ct |= TCG_CT_CONST_M12;
-        break;
-    case 'Z':
-        /* we can use a zero immediate as a zero register argument. */
-        ct->ct |= TCG_CT_CONST_ZERO;
-        break;
-    default:
-        return NULL;
-    }
-    return ct_str;
-}
-
 /* test if a constant matches the constraint */
 static int tcg_target_const_match(tcg_target_long val, TCGType type,
                                   const TCGArgConstraint *arg_ct)