| Message ID | 20210109143637.29645-1-bmeng.cn@gmail.com |
|---|---|
| State | New |
| Headers | show |
| Series | hw/riscv: sifive_u: Use SIFIVE_U_CPU for mc->default_cpu_type | expand |
On 1/9/21 3:36 PM, Bin Meng wrote: > From: Bin Meng <bin.meng@windriver.com> > > SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence > there is no need to use #idef to set the mc->default_cpu_type. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> > --- > > hw/riscv/sifive_u.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
On Sat, Jan 9, 2021 at 6:37 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence > there is no need to use #idef to set the mc->default_cpu_type. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> Reviewed-by: Alistair Francis <alistair.francis@wdc.com> Alistair > --- > > hw/riscv/sifive_u.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index f5c400dd44..e083510e0e 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -628,11 +628,7 @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data) > mc->init = sifive_u_machine_init; > mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; > mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; > -#if defined(TARGET_RISCV32) > - mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34; > -#elif defined(TARGET_RISCV64) > - mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54; > -#endif > + mc->default_cpu_type = SIFIVE_U_CPU; > mc->default_cpus = mc->min_cpus; > > object_class_property_add_bool(oc, "start-in-flash", > -- > 2.25.1 > >
On Sat, Jan 9, 2021 at 6:37 AM Bin Meng <bmeng.cn@gmail.com> wrote: > > From: Bin Meng <bin.meng@windriver.com> > > SIFIVE_U_CPU is conditionally set to SIFIVE_U34 or SIFIVE_U54, hence > there is no need to use #idef to set the mc->default_cpu_type. > > Signed-off-by: Bin Meng <bin.meng@windriver.com> Thanks! Applied to riscv-to-apply.next Alistair > --- > > hw/riscv/sifive_u.c | 6 +----- > 1 file changed, 1 insertion(+), 5 deletions(-) > > diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c > index f5c400dd44..e083510e0e 100644 > --- a/hw/riscv/sifive_u.c > +++ b/hw/riscv/sifive_u.c > @@ -628,11 +628,7 @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data) > mc->init = sifive_u_machine_init; > mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; > mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; > -#if defined(TARGET_RISCV32) > - mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34; > -#elif defined(TARGET_RISCV64) > - mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54; > -#endif > + mc->default_cpu_type = SIFIVE_U_CPU; > mc->default_cpus = mc->min_cpus; > > object_class_property_add_bool(oc, "start-in-flash", > -- > 2.25.1 > >
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index f5c400dd44..e083510e0e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -628,11 +628,7 @@ static void sifive_u_machine_class_init(ObjectClass *oc, void *data) mc->init = sifive_u_machine_init; mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; -#if defined(TARGET_RISCV32) - mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U34; -#elif defined(TARGET_RISCV64) - mc->default_cpu_type = TYPE_RISCV_CPU_SIFIVE_U54; -#endif + mc->default_cpu_type = SIFIVE_U_CPU; mc->default_cpus = mc->min_cpus; object_class_property_add_bool(oc, "start-in-flash",