| Message ID | 907e6379ae5fc8f5decdb344485123425de7afc1.1609306622.git.vijayakannan.ayyathurai@intel.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add drivers for Intel Keem Bay SoC timer block | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | fail | build log |
On Wed, 30 Dec 2020 14:25:26 +0800, vijayakannan.ayyathurai@intel.com wrote: > From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> > > Add Device Tree bindings for the Timer IP, which used as clocksource and > clockevent device in the Intel Keem Bay SoC. > > Acked-by: Mark Gross <mgross@linux.intel.com> > Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > Signed-off-by: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> > --- > .../bindings/timer/intel,keembay-timer.yaml | 52 +++++++++++++++++++ > 1 file changed, 52 insertions(+) > create mode 100644 Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > My bot found errors running 'make dt_binding_check' on your patch: yamllint warnings/errors: dtschema/dtc warnings/errors: Error: Documentation/devicetree/bindings/timer/intel,keembay-timer.example.dts:32.3-33.1 syntax error FATAL ERROR: Unable to parse input tree make[1]: *** [scripts/Makefile.lib:344: Documentation/devicetree/bindings/timer/intel,keembay-timer.example.dt.yaml] Error 1 make: *** [Makefile:1370: dt_binding_check] Error 2 See https://patchwork.ozlabs.org/patch/1421313 This check can fail if there are any dependencies. The base for a patch series is generally the most recent rc1. If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure 'yamllint' is installed and dt-schema is up to date: pip3 install dtschema --upgrade Please check and re-submit.
Hi Rob, > From: Rob Herring <robh@kernel.org> > > From: Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> > > > > Add Device Tree bindings for the Timer IP, which used as clocksource and > > clockevent device in the Intel Keem Bay SoC. > > > > Acked-by: Mark Gross <mgross@linux.intel.com> > > Acked-by: Andy Shevchenko <andriy.shevchenko@linux.intel.com> > > Signed-off-by: Vijayakannan Ayyathurai > <vijayakannan.ayyathurai@intel.com> > > --- > > .../bindings/timer/intel,keembay-timer.yaml | 52 +++++++++++++++++++ > > 1 file changed, 52 insertions(+) > > create mode 100644 > Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml > > > > My bot found errors running 'make dt_binding_check' on your patch: > > yamllint warnings/errors: > > dtschema/dtc warnings/errors: > Error: Documentation/devicetree/bindings/timer/intel,keembay- > timer.example.dts:32.3-33.1 syntax error > FATAL ERROR: Unable to parse input tree > make[1]: *** [scripts/Makefile.lib:344: > Documentation/devicetree/bindings/timer/intel,keembay- > timer.example.dt.yaml] Error 1 > make: *** [Makefile:1370: dt_binding_check] Error 2 > > See https://patchwork.ozlabs.org/patch/1421313 > > This check can fail if there are any dependencies. The base for a patch > series is generally the most recent rc1. > > If you already ran 'make dt_binding_check' and didn't see the above > error(s), then make sure 'yamllint' is installed and dt-schema is up to > date: > > pip3 install dtschema --upgrade > > Please check and re-submit. Thanks for the review. Let me check again and re-submit in the next version. Thanks, Vijay
diff --git a/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml new file mode 100644 index 000000000000..197493336ac2 --- /dev/null +++ b/Documentation/devicetree/bindings/timer/intel,keembay-timer.yaml @@ -0,0 +1,52 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/timer/intel,keembay-timer.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Intel Keem Bay SoC Timers + +maintainers: + - Wan Ahmad Zainie <wan.ahmad.zainie.wan.mohamad@intel.com> + - Vijayakannan Ayyathurai <vijayakannan.ayyathurai@intel.com> + +description: + Intel Keem Bay SoC Timers block contains 8 32-bit general purpose timers, + a free running 64-bit counter, a random number generator and a watchdog + timer. Each gpt can generate an individual interrupt. + +properties: + compatible: + enum: + - intel,keembay-timer + + reg: + maxItems: 3 + + clocks: + maxItems: 1 + + interrupts: + maxItems: 1 + +required: + - compatible + - reg + - interrupts + - clocks + +additionalProperties: false + +examples: + - | + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + #define KEEM_BAY_A53_TIM + + timer@20330010 { + compatible = "intel,keembay-timer"; + reg = <0x20330010 0xc>, + <0x203300e8 0xc>, + <0x20331000 0xc>; + clocks = <&scmi_clk KEEM_BAY_A53_TIM>; + interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>;