| Message ID | 20201020053309.19542-1-pragnesh.patel@sifive.com |
|---|---|
| State | Accepted |
| Commit | 7257455e7cd8038263a738401cbfe0ee8a2c7ac9 |
| Delegated to: | Andes |
| Headers | show |
| Series | riscv: fu540: dts: Correct reg size of clint node | expand |
On Tue, Oct 20, 2020 at 1:33 PM Pragnesh Patel <pragnesh.patel@sifive.com> wrote: > > Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> > --- > arch/riscv/dts/fu540-c000-u-boot.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > Reviewed-by: Bin Meng <bin.meng@windriver.com>
> From: Pragnesh Patel [mailto:pragnesh.patel@sifive.com] > Sent: Tuesday, October 20, 2020 1:33 PM > To: u-boot@lists.denx.de; atish.patra@wdc.com; palmerdabbelt@google.com; bmeng.cn@gmail.com; paul.walmsley@sifive.com > Cc: anup.patel@wdc.com; sagar.kadam@sifive.com; Rick Jian-Zhi Chen(陳建志); Pragnesh Patel; Bin Meng; Jagan Teki; Sean Anderson > Subject: [PATCH] riscv: fu540: dts: Correct reg size of clint node > > Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> > --- > arch/riscv/dts/fu540-c000-u-boot.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) Reviewed-by: Rick Chen <rick@andestech.com>
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index a06e1b11c6..b7cd600b8c 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -62,7 +62,7 @@ &cpu2_intc 3 &cpu2_intc 7 &cpu3_intc 3 &cpu3_intc 7 &cpu4_intc 3 &cpu4_intc 7>; - reg = <0x0 0x2000000 0x0 0xc0000>; + reg = <0x0 0x2000000 0x0 0x10000>; u-boot,dm-spl; }; prci: clock-controller@10000000 {
Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> --- arch/riscv/dts/fu540-c000-u-boot.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)