| Message ID | 20200906154340.v3.2.I25148ea0707da6ca2a9c2a86cdaca2439052abac@changeid |
|---|---|
| State | Superseded |
| Delegated to: | Bin Meng |
| Headers | show |
| Series | dm: Add programatic generation of ACPI tables (part D) | expand |
Hi Simon, -----"Simon Glass" <sjg@chromium.org> schrieb: ----- > Betreff: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices > > Add common x86 ASL files, taken from coreboot. > > Signed-off-by: Simon Glass <sjg@chromium.org> > --- > > (no changes since v1) > > arch/x86/include/asm/acpi/chromeos.asl | 108 +++++++++++++++++ > arch/x86/include/asm/acpi/cpu.asl | 25 ++++ > arch/x86/include/asm/acpi/cros_gnvs.asl | 29 +++++ > arch/x86/include/asm/acpi/lpc.asl | 141 ++++++++++++++++++++++ > arch/x86/include/asm/acpi/pci_osc.asl | 21 ++++ > arch/x86/include/asm/acpi/pcr.asl | 80 ++++++++++++ > arch/x86/include/asm/acpi/ramoops.asl | 32 +++++ > arch/x86/include/asm/acpi/sleepstates.asl | 12 +- > 8 files changed, 443 insertions(+), 5 deletions(-) > create mode 100644 arch/x86/include/asm/acpi/chromeos.asl > create mode 100644 arch/x86/include/asm/acpi/cpu.asl > create mode 100644 arch/x86/include/asm/acpi/cros_gnvs.asl > create mode 100644 arch/x86/include/asm/acpi/lpc.asl > create mode 100644 arch/x86/include/asm/acpi/pci_osc.asl > create mode 100644 arch/x86/include/asm/acpi/pcr.asl > create mode 100644 arch/x86/include/asm/acpi/ramoops.asl There are recent (~June 2020) commits in coreboot which convert most ASL files to ASL 2.0. The ASL 2.0 syntax is much easier to read IMHO, and I think it would be good to update this patch to take advantage of the recent coreboot developments. See e.g. the commit at [1]. regards, Wolfgang [1] https://github.com/coreboot/coreboot/commit/03248033e7be6f81ad5b60ed21a60071aee32c67
Hi Wolfgang, On Mon, 21 Sep 2020 at 07:50, Wolfgang Wallner <wolfgang.wallner@br-automation.com> wrote: > > Hi Simon, > > -----"Simon Glass" <sjg@chromium.org> schrieb: ----- > > Betreff: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices > > > > Add common x86 ASL files, taken from coreboot. > > > > Signed-off-by: Simon Glass <sjg@chromium.org> > > --- > > > > (no changes since v1) > > > > arch/x86/include/asm/acpi/chromeos.asl | 108 +++++++++++++++++ > > arch/x86/include/asm/acpi/cpu.asl | 25 ++++ > > arch/x86/include/asm/acpi/cros_gnvs.asl | 29 +++++ > > arch/x86/include/asm/acpi/lpc.asl | 141 ++++++++++++++++++++++ > > arch/x86/include/asm/acpi/pci_osc.asl | 21 ++++ > > arch/x86/include/asm/acpi/pcr.asl | 80 ++++++++++++ > > arch/x86/include/asm/acpi/ramoops.asl | 32 +++++ > > arch/x86/include/asm/acpi/sleepstates.asl | 12 +- > > 8 files changed, 443 insertions(+), 5 deletions(-) > > create mode 100644 arch/x86/include/asm/acpi/chromeos.asl > > create mode 100644 arch/x86/include/asm/acpi/cpu.asl > > create mode 100644 arch/x86/include/asm/acpi/cros_gnvs.asl > > create mode 100644 arch/x86/include/asm/acpi/lpc.asl > > create mode 100644 arch/x86/include/asm/acpi/pci_osc.asl > > create mode 100644 arch/x86/include/asm/acpi/pcr.asl > > create mode 100644 arch/x86/include/asm/acpi/ramoops.asl > > There are recent (~June 2020) commits in coreboot which convert most ASL files > to ASL 2.0. The ASL 2.0 syntax is much easier to read IMHO, and I think it > would be good to update this patch to take advantage of the recent coreboot > developments. See e.g. the commit at [1]. Yes that looks nicer, but I have everything working and tested now so don't want to go back and unpick things. This seems like something we can pick up once we finally have this in the tree. The good thing is that this is just a syntax change as I understand it. A WFH project has been putting a few Chromebooks in my lab, and I expect to put coral in there once everything lands. That should give us the confidence to make minor and major changes in future. Regards, SImon > [1] https://github.com/coreboot/coreboot/commit/03248033e7be6f81ad5b60ed21a60071aee32c67 > > >
Hi Simon, -----"Simon Glass" <sjg@chromium.org> schrieb: ----- > Betreff: Re: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices > > Hi Wolfgang, > > On Mon, 21 Sep 2020 at 07:50, Wolfgang Wallner > <wolfgang.wallner@br-automation.com> wrote: > > > > Hi Simon, > > > > -----"Simon Glass" <sjg@chromium.org> schrieb: ----- > > > Betreff: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices > > > > > > Add common x86 ASL files, taken from coreboot. > > > > > > Signed-off-by: Simon Glass <sjg@chromium.org> > > > --- > > > > > > (no changes since v1) > > > > > > arch/x86/include/asm/acpi/chromeos.asl | 108 +++++++++++++++++ > > > arch/x86/include/asm/acpi/cpu.asl | 25 ++++ > > > arch/x86/include/asm/acpi/cros_gnvs.asl | 29 +++++ > > > arch/x86/include/asm/acpi/lpc.asl | 141 ++++++++++++++++++++++ > > > arch/x86/include/asm/acpi/pci_osc.asl | 21 ++++ > > > arch/x86/include/asm/acpi/pcr.asl | 80 ++++++++++++ > > > arch/x86/include/asm/acpi/ramoops.asl | 32 +++++ > > > arch/x86/include/asm/acpi/sleepstates.asl | 12 +- > > > 8 files changed, 443 insertions(+), 5 deletions(-) > > > create mode 100644 arch/x86/include/asm/acpi/chromeos.asl > > > create mode 100644 arch/x86/include/asm/acpi/cpu.asl > > > create mode 100644 arch/x86/include/asm/acpi/cros_gnvs.asl > > > create mode 100644 arch/x86/include/asm/acpi/lpc.asl > > > create mode 100644 arch/x86/include/asm/acpi/pci_osc.asl > > > create mode 100644 arch/x86/include/asm/acpi/pcr.asl > > > create mode 100644 arch/x86/include/asm/acpi/ramoops.asl > > > > There are recent (~June 2020) commits in coreboot which convert most ASL files > > to ASL 2.0. The ASL 2.0 syntax is much easier to read IMHO, and I think it > > would be good to update this patch to take advantage of the recent coreboot > > developments. See e.g. the commit at [1]. > > Yes that looks nicer, but I have everything working and tested now so > don't want to go back and unpick things. This seems like something we > can pick up once we finally have this in the tree. The good thing is > that this is just a syntax change as I understand it. Fair enough. Yes, it should only be a syntax change. Regardingn testing: I haven't tested individual patches of part D, but I have tested the complete series. After applying the fix for the DSDT length my ApolloLake board has booted reliably with ACPI enabled. I have some remaining issues that I haven't gone after yet (e.g. I see a machine check error in the log), but the board always boots. > A WFH project has been putting a few Chromebooks in my lab, and I > expect to put coral in there once everything lands. That should give > us the confidence to make minor and major changes in future. > > Regards, > SImon > > > [1] https://github.com/coreboot/coreboot/commit/03248033e7be6f81ad5b60ed21a60071aee32c67 > > regards, Wolfgang
Hi Wolfgang, On Tue, Sep 22, 2020 at 10:19 PM Wolfgang Wallner <wolfgang.wallner@br-automation.com> wrote: > > Hi Simon, > > -----"Simon Glass" <sjg@chromium.org> schrieb: ----- > > Betreff: Re: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices > > > > Hi Wolfgang, > > > > On Mon, 21 Sep 2020 at 07:50, Wolfgang Wallner > > <wolfgang.wallner@br-automation.com> wrote: > > > > > > Hi Simon, > > > > > > -----"Simon Glass" <sjg@chromium.org> schrieb: ----- > > > > Betreff: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices > > > > > > > > Add common x86 ASL files, taken from coreboot. > > > > > > > > Signed-off-by: Simon Glass <sjg@chromium.org> > > > > --- > > > > > > > > (no changes since v1) > > > > > > > > arch/x86/include/asm/acpi/chromeos.asl | 108 +++++++++++++++++ > > > > arch/x86/include/asm/acpi/cpu.asl | 25 ++++ > > > > arch/x86/include/asm/acpi/cros_gnvs.asl | 29 +++++ > > > > arch/x86/include/asm/acpi/lpc.asl | 141 ++++++++++++++++++++++ > > > > arch/x86/include/asm/acpi/pci_osc.asl | 21 ++++ > > > > arch/x86/include/asm/acpi/pcr.asl | 80 ++++++++++++ > > > > arch/x86/include/asm/acpi/ramoops.asl | 32 +++++ > > > > arch/x86/include/asm/acpi/sleepstates.asl | 12 +- > > > > 8 files changed, 443 insertions(+), 5 deletions(-) > > > > create mode 100644 arch/x86/include/asm/acpi/chromeos.asl > > > > create mode 100644 arch/x86/include/asm/acpi/cpu.asl > > > > create mode 100644 arch/x86/include/asm/acpi/cros_gnvs.asl > > > > create mode 100644 arch/x86/include/asm/acpi/lpc.asl > > > > create mode 100644 arch/x86/include/asm/acpi/pci_osc.asl > > > > create mode 100644 arch/x86/include/asm/acpi/pcr.asl > > > > create mode 100644 arch/x86/include/asm/acpi/ramoops.asl > > > > > > There are recent (~June 2020) commits in coreboot which convert most ASL files > > > to ASL 2.0. The ASL 2.0 syntax is much easier to read IMHO, and I think it > > > would be good to update this patch to take advantage of the recent coreboot > > > developments. See e.g. the commit at [1]. > > > > Yes that looks nicer, but I have everything working and tested now so > > don't want to go back and unpick things. This seems like something we > > can pick up once we finally have this in the tree. The good thing is > > that this is just a syntax change as I understand it. > > Fair enough. Yes, it should only be a syntax change. > > Regardingn testing: I haven't tested individual patches of part D, but I have > tested the complete series. After applying the fix for the DSDT length my > ApolloLake board has booted reliably with ACPI enabled. > Will you add the "Tested-by" tag for this series? BTW: any plan to upstream your board support? > I have some remaining issues that I haven't gone after yet (e.g. I see a > machine check error in the log), but the board always boots. > Regards, Bin
Hi Bin, -----"Bin Meng" <bmeng.cn@gmail.com> schrieb: ----- > Betreff: Re: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices > > Hi Wolfgang, > > On Tue, Sep 22, 2020 at 10:19 PM Wolfgang Wallner > <wolfgang.wallner@br-automation.com> wrote: > > > > Hi Simon, > > > > -----"Simon Glass" <sjg@chromium.org> schrieb: ----- > > > Betreff: Re: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices > > > > > > Hi Wolfgang, > > > > > > On Mon, 21 Sep 2020 at 07:50, Wolfgang Wallner > > > <wolfgang.wallner@br-automation.com> wrote: > > > > > > > > Hi Simon, > > > > > > > > -----"Simon Glass" <sjg@chromium.org> schrieb: ----- > > > > > Betreff: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices > > > > > > > > > > Add common x86 ASL files, taken from coreboot. > > > > > > > > > > Signed-off-by: Simon Glass <sjg@chromium.org> > > > > > --- > > > > > > > > > > (no changes since v1) > > > > > > > > > > arch/x86/include/asm/acpi/chromeos.asl | 108 +++++++++++++++++ > > > > > arch/x86/include/asm/acpi/cpu.asl | 25 ++++ > > > > > arch/x86/include/asm/acpi/cros_gnvs.asl | 29 +++++ > > > > > arch/x86/include/asm/acpi/lpc.asl | 141 ++++++++++++++++++++++ > > > > > arch/x86/include/asm/acpi/pci_osc.asl | 21 ++++ > > > > > arch/x86/include/asm/acpi/pcr.asl | 80 ++++++++++++ > > > > > arch/x86/include/asm/acpi/ramoops.asl | 32 +++++ > > > > > arch/x86/include/asm/acpi/sleepstates.asl | 12 +- > > > > > 8 files changed, 443 insertions(+), 5 deletions(-) > > > > > create mode 100644 arch/x86/include/asm/acpi/chromeos.asl > > > > > create mode 100644 arch/x86/include/asm/acpi/cpu.asl > > > > > create mode 100644 arch/x86/include/asm/acpi/cros_gnvs.asl > > > > > create mode 100644 arch/x86/include/asm/acpi/lpc.asl > > > > > create mode 100644 arch/x86/include/asm/acpi/pci_osc.asl > > > > > create mode 100644 arch/x86/include/asm/acpi/pcr.asl > > > > > create mode 100644 arch/x86/include/asm/acpi/ramoops.asl > > > > > > > > There are recent (~June 2020) commits in coreboot which convert most ASL files > > > > to ASL 2.0. The ASL 2.0 syntax is much easier to read IMHO, and I think it > > > > would be good to update this patch to take advantage of the recent coreboot > > > > developments. See e.g. the commit at [1]. > > > > > > Yes that looks nicer, but I have everything working and tested now so > > > don't want to go back and unpick things. This seems like something we > > > can pick up once we finally have this in the tree. The good thing is > > > that this is just a syntax change as I understand it. > > > > Fair enough. Yes, it should only be a syntax change. > > > > Regardingn testing: I haven't tested individual patches of part D, but I have > > tested the complete series. After applying the fix for the DSDT length my > > ApolloLake board has booted reliably with ACPI enabled. > > > > Will you add the "Tested-by" tag for this series? I lack experience in testing complete series, which is why I was not sure how this should be handled. If testing a complete series at once is enough, without testing the individual patches, then this series is: Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> Tested on a custom ApolloLake board. > BTW: any plan to upstream your board support? Yes, that would be one of the long term goals. regards, Wolfgang
Hi Wolfgang, On Tue, Sep 22, 2020 at 10:47 PM Wolfgang Wallner <wolfgang.wallner@br-automation.com> wrote: > > Hi Bin, > > -----"Bin Meng" <bmeng.cn@gmail.com> schrieb: ----- > > Betreff: Re: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices > > > > Hi Wolfgang, > > > > On Tue, Sep 22, 2020 at 10:19 PM Wolfgang Wallner > > <wolfgang.wallner@br-automation.com> wrote: > > > > > > Hi Simon, > > > > > > -----"Simon Glass" <sjg@chromium.org> schrieb: ----- > > > > Betreff: Re: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices > > > > > > > > Hi Wolfgang, > > > > > > > > On Mon, 21 Sep 2020 at 07:50, Wolfgang Wallner > > > > <wolfgang.wallner@br-automation.com> wrote: > > > > > > > > > > Hi Simon, > > > > > > > > > > -----"Simon Glass" <sjg@chromium.org> schrieb: ----- > > > > > > Betreff: [PATCH v3 02/57] x86: acpi: Add base asl files for common x86 devices > > > > > > > > > > > > Add common x86 ASL files, taken from coreboot. > > > > > > > > > > > > Signed-off-by: Simon Glass <sjg@chromium.org> > > > > > > --- > > > > > > > > > > > > (no changes since v1) > > > > > > > > > > > > arch/x86/include/asm/acpi/chromeos.asl | 108 +++++++++++++++++ > > > > > > arch/x86/include/asm/acpi/cpu.asl | 25 ++++ > > > > > > arch/x86/include/asm/acpi/cros_gnvs.asl | 29 +++++ > > > > > > arch/x86/include/asm/acpi/lpc.asl | 141 ++++++++++++++++++++++ > > > > > > arch/x86/include/asm/acpi/pci_osc.asl | 21 ++++ > > > > > > arch/x86/include/asm/acpi/pcr.asl | 80 ++++++++++++ > > > > > > arch/x86/include/asm/acpi/ramoops.asl | 32 +++++ > > > > > > arch/x86/include/asm/acpi/sleepstates.asl | 12 +- > > > > > > 8 files changed, 443 insertions(+), 5 deletions(-) > > > > > > create mode 100644 arch/x86/include/asm/acpi/chromeos.asl > > > > > > create mode 100644 arch/x86/include/asm/acpi/cpu.asl > > > > > > create mode 100644 arch/x86/include/asm/acpi/cros_gnvs.asl > > > > > > create mode 100644 arch/x86/include/asm/acpi/lpc.asl > > > > > > create mode 100644 arch/x86/include/asm/acpi/pci_osc.asl > > > > > > create mode 100644 arch/x86/include/asm/acpi/pcr.asl > > > > > > create mode 100644 arch/x86/include/asm/acpi/ramoops.asl > > > > > > > > > > There are recent (~June 2020) commits in coreboot which convert most ASL files > > > > > to ASL 2.0. The ASL 2.0 syntax is much easier to read IMHO, and I think it > > > > > would be good to update this patch to take advantage of the recent coreboot > > > > > developments. See e.g. the commit at [1]. > > > > > > > > Yes that looks nicer, but I have everything working and tested now so > > > > don't want to go back and unpick things. This seems like something we > > > > can pick up once we finally have this in the tree. The good thing is > > > > that this is just a syntax change as I understand it. > > > > > > Fair enough. Yes, it should only be a syntax change. > > > > > > Regardingn testing: I haven't tested individual patches of part D, but I have > > > tested the complete series. After applying the fix for the DSDT length my > > > ApolloLake board has booted reliably with ACPI enabled. > > > > > > > Will you add the "Tested-by" tag for this series? > > I lack experience in testing complete series, which is why I was not sure how > this should be handled. If testing a complete series at once is enough, without > testing the individual patches, then this series is: > > Tested-by: Wolfgang Wallner <wolfgang.wallner@br-automation.com> > Tested on a custom ApolloLake board. Thank you. But I will leave Simon to pick up the tag in the next version whenever it makes sense. > > > BTW: any plan to upstream your board support? > > Yes, that would be one of the long term goals. Great! Regards, Bin
diff --git a/arch/x86/include/asm/acpi/chromeos.asl b/arch/x86/include/asm/acpi/chromeos.asl new file mode 100644 index 00000000000..2a0fd33265d --- /dev/null +++ b/arch/x86/include/asm/acpi/chromeos.asl @@ -0,0 +1,108 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. + */ + +#ifdef CONFIG_CHROMEOS + +#define CONFIG_VBOOT_VBNV_OFFSET 0x26 + +#include <asm/acpi/vbnv_layout.h> + +/* GPIO package generated at run time. */ +External (OIPG) + +Device (CRHW) +{ + Name(_HID, EISAID("GGL0001")) + + Method(_STA, 0, Serialized) + { + Return (0xb) + } + + Method(CHSW, 0, Serialized) + { + Name (WSHC, Package() { VBT3 }) + Return (WSHC) + } + + Method(FWID, 0, Serialized) + { + Name (DIW1, "") + ToString(VBT5, 63, DIW1) + Name (DIWF, Package() { DIW1 }) + Return(DIWF) + } + + Method(FRID, 0, Serialized) + { + Name (DIR1, "") + ToString(VBT6, 63, DIR1) + Name (DIRF, Package() { DIR1 }) + Return (DIRF) + } + + Method(HWID, 0, Serialized) + { + Name (DIW0, "") + ToString(VBT4, 255, DIW0) + Name (DIWH, Package() { DIW0 }) + Return (DIWH) + } + + Method(BINF, 0, Serialized) + { + Name (FNIB, Package() { VBT0, VBT1, VBT2, VBT7, VBT8 }) + Return (FNIB) + } + + Method(GPIO, 0, Serialized) + { + Return (OIPG) + + } + + Method(VBNV, 0, Serialized) + { + Name(VNBV, Package() { + // See src/vendorcode/google/chromeos/Kconfig + // for the definition of these: + CONFIG_VBOOT_VBNV_OFFSET, + VBOOT_VBNV_BLOCK_SIZE + }) + Return(VNBV) + } + + Method(VDAT, 0, Serialized) + { + Name(TAD0,"") + ToBuffer(CHVD, TAD0) + Name (TADV, Package() { TAD0 }) + Return (TADV) + } + + Method(FMAP, 0, Serialized) + { + Name(PAMF, Package() { VBT9 }) + Return(PAMF) + } + + Method(MECK, 0, Serialized) + { + Name(HASH, Package() { MEHH }) + Return(HASH) + } + + Method(MLST, 0, Serialized) + { + Name(TSLM, Package() { "CHSW", "FWID", "HWID", "FRID", "BINF", + "GPIO", "VBNV", "VDAT", "FMAP", "MECK" + }) + Return (TSLM) + } +} + +#include "ramoops.asl" + +#endif diff --git a/arch/x86/include/asm/acpi/cpu.asl b/arch/x86/include/asm/acpi/cpu.asl new file mode 100644 index 00000000000..b20b3572f2b --- /dev/null +++ b/arch/x86/include/asm/acpi/cpu.asl @@ -0,0 +1,25 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +/* These come from the dynamically created CPU SSDT */ +External (\_PR.CNOT, MethodObj) + +/* Notify OS to re-read CPU tables */ +Method (PNOT) +{ + \_PR.CNOT (0x81) +} + +/* Notify OS to re-read CPU _PPC limit */ +Method (PPCN) +{ + \_PR.CNOT (0x80) +} + +/* Notify OS to re-read Throttle Limit tables */ +Method (TNOT) +{ + \_PR.CNOT (0x82) +} diff --git a/arch/x86/include/asm/acpi/cros_gnvs.asl b/arch/x86/include/asm/acpi/cros_gnvs.asl new file mode 100644 index 00000000000..c20b64565e0 --- /dev/null +++ b/arch/x86/include/asm/acpi/cros_gnvs.asl @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright 2019 Google LLC + */ + +/* This is the ChromeOS specific ACPI information needed by + * the mainboard's chromeos.asl + */ + +VBT0, 32, // 0x000 - Boot Reason +VBT1, 32, // 0x004 - Active Main Firmware +VBT2, 32, // 0x008 - Active EC Firmware +VBT3, 16, // 0x00c - CHSW +VBT4, 2048, // 0x00e - HWID +VBT5, 512, // 0x10e - FWID +VBT6, 512, // 0x14e - FRID +VBT7, 32, // 0x18e - active main firmware type +VBT8, 32, // 0x192 - Recovery Reason +VBT9, 32, // 0x196 - FMAP base address +CHVD, 24576, // 0x19a - VDAT space filled by verified boot +VBTA, 32, // 0xd9a - pointer to smbios FWID +MEHH, 256, // 0xd9e - Management Engine Hash +RMOB, 32, // 0xdbe - RAM oops base address +RMOL, 32, // 0xdc2 - RAM oops length +ROVP, 32, // 0xdc6 - pointer to RO_VPD +ROVL, 32, // 0xdca - size of RO_VPD +RWVP, 32, // 0xdce - pointer to RW_VPD +RWVL, 32, // 0xdd2 - size of RW_VPD + // 0xdd6 diff --git a/arch/x86/include/asm/acpi/lpc.asl b/arch/x86/include/asm/acpi/lpc.asl new file mode 100644 index 00000000000..18cc78b3e14 --- /dev/null +++ b/arch/x86/include/asm/acpi/lpc.asl @@ -0,0 +1,141 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + */ + +/* Intel LPC/eSPI Bus Device - 0:1f.0 */ +#include <asm/arch/iomap.h> + +Device (LPCB) +{ + Name (_ADR, 0x001f0000) + Name (_DDN, "LPC Bus Device") + + /* DMA Controller */ + Device (DMAC) + { + Name (_HID, EISAID("PNP0200")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x00, 0x00, 0x01, 0x20) + IO (Decode16, 0x81, 0x81, 0x01, 0x11) + IO (Decode16, 0x93, 0x93, 0x01, 0x0d) + IO (Decode16, 0xc0, 0xc0, 0x01, 0x20) + DMA (Compatibility, NotBusMaster, Transfer8_16) { 4 } + }) + } + + /* Firmware Hub */ + Device (FWH) + { + Name (_HID, EISAID ("INT0800")) + Name (_DDN, "Firmware Hub") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadOnly, 0xff000000, 0x01000000) + }) + } + + /* High Precision Event Timer */ + Device (HPET) + { + Name (_HID, EISAID ("PNP0103")) + Name (_CID, 0x010CD041) + Name (_DDN, "High Precision Event Timer") + Name (_CRS, ResourceTemplate () + { + Memory32Fixed (ReadWrite, HPET_BASE_ADDRESS, 0x400) + }) + Method (_STA, 0) + { + Return (0xF) + } + } + + /* FPU */ + Device(MATH) + { + Name (_HID, EISAID("PNP0C04")) + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0xf0, 0xf0, 0x01, 0x01) + IRQNoFlags() { 13 } + }) + } + + /* AT Interrupt Controller */ + Device (PIC) + { + Name (_HID, EISAID ("PNP0000")) + Name (_DDN, "8259 Interrupt Controller") + Name (_CRS, ResourceTemplate() + { + IO (Decode16, 0x20, 0x20, 0x01, 0x02) + IO (Decode16, 0x24, 0x24, 0x01, 0x02) + IO (Decode16, 0x28, 0x28, 0x01, 0x02) + IO (Decode16, 0x2c, 0x2c, 0x01, 0x02) + IO (Decode16, 0x30, 0x30, 0x01, 0x02) + IO (Decode16, 0x34, 0x34, 0x01, 0x02) + IO (Decode16, 0x38, 0x38, 0x01, 0x02) + IO (Decode16, 0x3c, 0x3c, 0x01, 0x02) + IO (Decode16, 0xa0, 0xa0, 0x01, 0x02) + IO (Decode16, 0xa4, 0xa4, 0x01, 0x02) + IO (Decode16, 0xa8, 0xa8, 0x01, 0x02) + IO (Decode16, 0xac, 0xac, 0x01, 0x02) + IO (Decode16, 0xb0, 0xb0, 0x01, 0x02) + IO (Decode16, 0xb4, 0xb4, 0x01, 0x02) + IO (Decode16, 0xb8, 0xb8, 0x01, 0x02) + IO (Decode16, 0xbc, 0xbc, 0x01, 0x02) + IO (Decode16, 0x4d0, 0x4d0, 0x01, 0x02) + IRQNoFlags () { 2 } + }) + } + + /* LPC device: Resource consumption */ + Device (LDRC) + { + Name (_HID, EISAID ("PNP0C02")) + Name (_UID, 2) + Name (_DDN, "Legacy Device Resources") + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x2e, 0x2e, 0x1, 0x02) // First SuperIO + IO (Decode16, 0x4e, 0x4e, 0x1, 0x02) // Second SuperIO + IO (Decode16, 0x61, 0x61, 0x1, 0x01) // NMI Status + IO (Decode16, 0x63, 0x63, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x65, 0x65, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x67, 0x67, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0x80, 0x80, 0x1, 0x01) // Port 80 Post + IO (Decode16, 0x92, 0x92, 0x1, 0x01) // CPU Reserved + IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI + IO (Decode16, ACPI_BASE_ADDRESS, ACPI_BASE_ADDRESS, + 0x1, 0xff) + }) + } + + /* Real Time Clock Device */ + Device (RTC) + { + Name (_HID, EISAID ("PNP0B00")) + Name (_DDN, "Real Time Clock") + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x70, 0x70, 1, 8) + }) + } + + /* Timer */ + Device (TIMR) + { + Name (_HID, EISAID ("PNP0100")) + Name (_DDN, "8254 Timer") + Name (_CRS, ResourceTemplate () + { + IO (Decode16, 0x40, 0x40, 0x01, 0x04) + IO (Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags () {0} + }) + } +} diff --git a/arch/x86/include/asm/acpi/pci_osc.asl b/arch/x86/include/asm/acpi/pci_osc.asl new file mode 100644 index 00000000000..864556fa831 --- /dev/null +++ b/arch/x86/include/asm/acpi/pci_osc.asl @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2016 Intel Corp. + */ + +#define PCI_OSC_UUID "33DB4D5B-1FF7-401C-9657-7441C03DD766" + +Scope (\_SB.PCI0) { + Method (_OSC, 4) { + /* Check for proper GUID */ + If (LEqual (Arg0, ToUUID (PCI_OSC_UUID))) { + /* Let OS control everything */ + Return (Arg3) + } Else { + /* Unrecognized UUID */ + CreateDWordField (Arg3, 0, CDW1) + Or (CDW1, 4, CDW1) + Return (Arg3) + } + } +} diff --git a/arch/x86/include/asm/acpi/pcr.asl b/arch/x86/include/asm/acpi/pcr.asl new file mode 100644 index 00000000000..f66737b89c1 --- /dev/null +++ b/arch/x86/include/asm/acpi/pcr.asl @@ -0,0 +1,80 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2015 Google Inc. + * Copyright (C) 2018 Intel Corporation. + */ + +#include <intelblocks/pcr.h> + +/* + * Calculate PCR register base at specified PID + * Arg0 - PCR Port ID + */ +Method (PCRB, 1, NotSerialized) +{ + Return (Add (IOMAP_P2SB_BAR, + ShiftLeft (Arg0, PCR_PORTID_SHIFT))) +} + +/* + * Read a PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + */ +Method (PCRR, 2, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + Return (DATA) +} + +/* + * AND a value with PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + * Arg2 - Value to AND + */ +Method (PCRA, 3, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + And (DATA, Arg2, DATA) + + /* + * After every write one needs to read an innocuous register + * to ensure the writes are completed for certain ports. This is done + * for all ports so that the callers don't need the per-port knowledge + * for each transaction. + */ + PCRR (Arg0, Arg1) +} + +/* + * OR a value with PCR register at specified PID and offset + * Arg0 - PCR Port ID + * Arg1 - Register Offset + * Arg2 - Value to OR + */ +Method (PCRO, 3, Serialized) +{ + OperationRegion (PCRD, SystemMemory, Add (PCRB (Arg0), Arg1), 4) + Field (PCRD, DWordAcc, NoLock, Preserve) + { + DATA, 32 + } + Or (DATA, Arg2, DATA) + + /* + * After every write one needs to read an innocuous register + * to ensure the writes are completed for certain ports. This is done + * for all ports so that the callers don't need the per-port knowledge + * for each transaction. + */ + PCRR (Arg0, Arg1) +} diff --git a/arch/x86/include/asm/acpi/ramoops.asl b/arch/x86/include/asm/acpi/ramoops.asl new file mode 100644 index 00000000000..55939e1aa33 --- /dev/null +++ b/arch/x86/include/asm/acpi/ramoops.asl @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* + * Copyright (C) 2014 Google Inc. + */ + +Scope (\_SB) +{ + Device(RMOP) + { + Name (_HID, "GOOG9999") + Name (_CID, "GOOG9999") + Name (_UID, 1) + + Name (RBUF, ResourceTemplate() + { + Memory32Fixed (ReadWrite, 0, 0, MRES) + }) + + Method (_CRS) + { + CreateDwordField (^RBUF, ^MRES._BAS, RBAS) + CreateDwordField (^RBUF, ^MRES._LEN, RLEN) + Store (\RMOB, RBAS) + Store (\RMOL, RLEN) + Return (^RBUF) + } + Method(_STA, 0) + { + Return (0xB) + } + } +} diff --git a/arch/x86/include/asm/acpi/sleepstates.asl b/arch/x86/include/asm/acpi/sleepstates.asl index 32e16a2c2f5..31aa69a5704 100644 --- a/arch/x86/include/asm/acpi/sleepstates.asl +++ b/arch/x86/include/asm/acpi/sleepstates.asl @@ -6,9 +6,11 @@ * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl */ -Name(\_S0, Package() {0x0, 0x0, 0x0, 0x0}) -#ifdef CONFIG_HAVE_ACPI_RESUME -Name(\_S3, Package() {0x5, 0x0, 0x0, 0x0}) +Name(\_S0, Package(){0x0,0x0,0x0,0x0}) +#if !IS_ENABLED(CONFIG_HAVE_ACPI_RESUME) +Name(\_S1, Package(){0x1,0x0,0x0,0x0}) +#else +Name(\_S3, Package(){0x5,0x0,0x0,0x0}) #endif -Name(\_S4, Package() {0x6, 0x0, 0x0, 0x0}) -Name(\_S5, Package() {0x7, 0x0, 0x0, 0x0}) +Name(\_S4, Package(){0x6,0x0,0x0,0x0}) +Name(\_S5, Package(){0x7,0x0,0x0,0x0})
Add common x86 ASL files, taken from coreboot. Signed-off-by: Simon Glass <sjg@chromium.org> --- (no changes since v1) arch/x86/include/asm/acpi/chromeos.asl | 108 +++++++++++++++++ arch/x86/include/asm/acpi/cpu.asl | 25 ++++ arch/x86/include/asm/acpi/cros_gnvs.asl | 29 +++++ arch/x86/include/asm/acpi/lpc.asl | 141 ++++++++++++++++++++++ arch/x86/include/asm/acpi/pci_osc.asl | 21 ++++ arch/x86/include/asm/acpi/pcr.asl | 80 ++++++++++++ arch/x86/include/asm/acpi/ramoops.asl | 32 +++++ arch/x86/include/asm/acpi/sleepstates.asl | 12 +- 8 files changed, 443 insertions(+), 5 deletions(-) create mode 100644 arch/x86/include/asm/acpi/chromeos.asl create mode 100644 arch/x86/include/asm/acpi/cpu.asl create mode 100644 arch/x86/include/asm/acpi/cros_gnvs.asl create mode 100644 arch/x86/include/asm/acpi/lpc.asl create mode 100644 arch/x86/include/asm/acpi/pci_osc.asl create mode 100644 arch/x86/include/asm/acpi/pcr.asl create mode 100644 arch/x86/include/asm/acpi/ramoops.asl