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[v2,2/7] riscv: Match memory barriers between send_ipi_many and handle_ipi

Message ID 20200914142303.21307-3-seanga2@gmail.com
State Superseded
Delegated to: Andes
Headers show
Series riscv: Correctly handle IPIs already pending upon boot | expand

Commit Message

Sean Anderson Sept. 14, 2020, 2:22 p.m. UTC 
Without a matching barrier on the write side, the barrier in handle_ipi
does nothing. It was entirely possible for the boot hart to write to addr,
arg0, and arg1 *after* sending the IPI, because there was no barrier on the
sending side.

Fixes: 90ae281437 ("riscv: add option to wait for ack from secondary harts in smp functions")
Signed-off-by: Sean Anderson <seanga2@gmail.com>
Reviewed-by: Bin Meng <bin.meng@windriver.com>
---

(no changes since v1)

 arch/riscv/lib/smp.c | 2 ++
 1 file changed, 2 insertions(+)

Comments

Rick Chen Sept. 15, 2020, 8:40 a.m. UTC | #1 
> Without a matching barrier on the write side, the barrier in handle_ipi
> does nothing. It was entirely possible for the boot hart to write to addr,
> arg0, and arg1 *after* sending the IPI, because there was no barrier on the
> sending side.
>
> Fixes: 90ae281437 ("riscv: add option to wait for ack from secondary harts in smp functions")
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> ---
>
> (no changes since v1)
>
>  arch/riscv/lib/smp.c | 2 ++
>  1 file changed, 2 insertions(+)
>

Reviewed-by: Rick Chen <rick@andestech.com>

> diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
> index ac22136314..ab6d8bd7fa 100644
> --- a/arch/riscv/lib/smp.c
> +++ b/arch/riscv/lib/smp.c
> @@ -54,6 +54,8 @@ static int send_ipi_many(struct ipi_data *ipi, int wait)
>                 gd->arch.ipi[reg].arg0 = ipi->arg0;
>                 gd->arch.ipi[reg].arg1 = ipi->arg1;
>
> +               __smp_mb();
> +
>                 ret = riscv_send_ipi(reg);
>                 if (ret) {
>                         pr_err("Cannot send IPI to hart %d\n", reg);
> --
> 2.28.0
>
Leo Liang Sept. 17, 2020, 11:12 a.m. UTC | #2 
On Mon, Sep 14, 2020 at 10:22:58AM -0400, Sean Anderson wrote:
> Without a matching barrier on the write side, the barrier in handle_ipi
> does nothing. It was entirely possible for the boot hart to write to addr,
> arg0, and arg1 *after* sending the IPI, because there was no barrier on the
> sending side.
> 
> Fixes: 90ae281437 ("riscv: add option to wait for ack from secondary harts in smp functions")
> Signed-off-by: Sean Anderson <seanga2@gmail.com>
> Reviewed-by: Bin Meng <bin.meng@windriver.com>
> Reviewed-by: Rick Chen <rick@andestech.com>
> ---
> 
> (no changes since v1)
> 
>  arch/riscv/lib/smp.c | 2 ++
>  1 file changed, 2 insertions(+)
> 
> diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
> index ac22136314..ab6d8bd7fa 100644
> --- a/arch/riscv/lib/smp.c
> +++ b/arch/riscv/lib/smp.c
> @@ -54,6 +54,8 @@ static int send_ipi_many(struct ipi_data *ipi, int wait)
>  		gd->arch.ipi[reg].arg0 = ipi->arg0;
>  		gd->arch.ipi[reg].arg1 = ipi->arg1;
>  
> +		__smp_mb();
> +
>  		ret = riscv_send_ipi(reg);
>  		if (ret) {
>  			pr_err("Cannot send IPI to hart %d\n", reg);

Reviewed-by: Leo Liang <ycliang@andestech.com>
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Patch

diff --git a/arch/riscv/lib/smp.c b/arch/riscv/lib/smp.c
index ac22136314..ab6d8bd7fa 100644
--- a/arch/riscv/lib/smp.c
+++ b/arch/riscv/lib/smp.c
@@ -54,6 +54,8 @@  static int send_ipi_many(struct ipi_data *ipi, int wait)
 		gd->arch.ipi[reg].arg0 = ipi->arg0;
 		gd->arch.ipi[reg].arg1 = ipi->arg1;
 
+		__smp_mb();
+
 		ret = riscv_send_ipi(reg);
 		if (ret) {
 			pr_err("Cannot send IPI to hart %d\n", reg);