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[v2,0/6] Add RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs

Message ID cover.1592941257.git.cristian.ciocaltea@gmail.com
Headers show
Series Add RMU and DMAC/GPIO clock support for Actions Semi S500 SoCs | expand

Message

Cristian Ciocaltea June 24, 2020, 5:47 p.m. UTC 
This patch series is a stripped-down revision of the initial series
"[PATCH 00/11] Add CMU/RMU/DMA support for Actions Semi S500 SoCs":
https://lore.kernel.org/lkml/cover.1592407030.git.cristian.ciocaltea@gmail.com/

At Stephen's request, I detached all DTS related work to keep the focus
exclusively on the Actions S500 SoC clock driver changes:

 - Add support for some missing clocks: APB, DMAC, GPIO
 - Add support for Reset Management Unit

The removed patches are subject to resubmission via a separate series:

 - arm: dts: owl-s500: Add Clock Management Unit
 - arm: dts: owl-s500: Set UART clock refs from CMU
 - arm: dts: owl-s500-roseapplepi: Use UART clock from CMU
 - arm: dts: owl-s500: Add DMA controller
 - arm: dts: owl-s500: Add Reset Controller support

Regards,
Cristi

Changes in v1:
 - Incorporate Stephen's review comments
 - Remove DTS related patches
 - Rebase remaining patches on v5.8-rc2
 - Update cover letter, both subject and content, to reflect the new
   scope

Cristian Ciocaltea (6):
  clk: actions: Fix h_clk for Actions S500 SoC
  dt-bindings: clock: Add APB, DMAC, GPIO bindings for Actions S500 SoC
  clk: actions: Add APB, DMAC, GPIO clock support for Actions S500 SoC
  dt-bindings: reset: Add binding constants for Actions S500 RMU
  clk: actions: Add Actions S500 SoC Reset Management Unit support
  MAINTAINERS: Add reset binding entry for Actions Semi Owl SoCs

 MAINTAINERS                                   |  1 +
 drivers/clk/actions/owl-s500.c                | 89 ++++++++++++++++++-
 include/dt-bindings/clock/actions,s500-cmu.h  | 77 ++++++++--------
 .../dt-bindings/reset/actions,s500-reset.h    | 67 ++++++++++++++
 4 files changed, 196 insertions(+), 38 deletions(-)
 create mode 100644 include/dt-bindings/reset/actions,s500-reset.h

Comments

Manivannan Sadhasivam June 26, 2020, 1:45 p.m. UTC | #1 
On Wed, Jun 24, 2020 at 08:47:52PM +0300, Cristian Ciocaltea wrote:
> The h_clk clock in the Actions Semi S500 SoC clock driver has an
> invalid parent. Replace with the correct one.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

You should add fixes tag for this patch and it needs to be backported as well.

Thanks,
Mani

> ---
>  drivers/clk/actions/owl-s500.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
> index e2007ac4d235..0eb83a0b70bc 100644
> --- a/drivers/clk/actions/owl-s500.c
> +++ b/drivers/clk/actions/owl-s500.c
> @@ -183,7 +183,7 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
>  static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
>  
>  /* divider clocks */
> -static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> +static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
>  static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
>  
>  /* factor clocks */
> -- 
> 2.27.0
>
Manivannan Sadhasivam June 26, 2020, 1:52 p.m. UTC | #2 
On Wed, Jun 24, 2020 at 08:47:56PM +0300, Cristian Ciocaltea wrote:
> Add Reset Management Unit (RMU) support for Actions Semi S500 SoC.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>

Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>

Thanks,
Mani

> ---
> Changes in v2:
>  - Remove copyright as indicated by Stephen
> 
>  drivers/clk/actions/owl-s500.c | 78 ++++++++++++++++++++++++++++++++++
>  1 file changed, 78 insertions(+)
> 
> diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
> index 025a8f6d6482..61bb224f6330 100644
> --- a/drivers/clk/actions/owl-s500.c
> +++ b/drivers/clk/actions/owl-s500.c
> @@ -23,8 +23,10 @@
>  #include "owl-gate.h"
>  #include "owl-mux.h"
>  #include "owl-pll.h"
> +#include "owl-reset.h"
>  
>  #include <dt-bindings/clock/actions,s500-cmu.h>
> +#include <dt-bindings/reset/actions,s500-reset.h>
>  
>  #define CMU_COREPLL			(0x0000)
>  #define CMU_DEVPLL			(0x0004)
> @@ -497,20 +499,96 @@ static struct clk_hw_onecell_data s500_hw_clks = {
>  	.num = CLK_NR_CLKS,
>  };
>  
> +static const struct owl_reset_map s500_resets[] = {
> +	[RESET_DMAC]	= { CMU_DEVRST0, BIT(0) },
> +	[RESET_NORIF]	= { CMU_DEVRST0, BIT(1) },
> +	[RESET_DDR]	= { CMU_DEVRST0, BIT(2) },
> +	[RESET_NANDC]	= { CMU_DEVRST0, BIT(3) },
> +	[RESET_SD0]	= { CMU_DEVRST0, BIT(4) },
> +	[RESET_SD1]	= { CMU_DEVRST0, BIT(5) },
> +	[RESET_PCM1]	= { CMU_DEVRST0, BIT(6) },
> +	[RESET_DE]	= { CMU_DEVRST0, BIT(7) },
> +	[RESET_LCD]	= { CMU_DEVRST0, BIT(8) },
> +	[RESET_SD2]	= { CMU_DEVRST0, BIT(9) },
> +	[RESET_DSI]	= { CMU_DEVRST0, BIT(10) },
> +	[RESET_CSI]	= { CMU_DEVRST0, BIT(11) },
> +	[RESET_BISP]	= { CMU_DEVRST0, BIT(12) },
> +	[RESET_KEY]	= { CMU_DEVRST0, BIT(14) },
> +	[RESET_GPIO]	= { CMU_DEVRST0, BIT(15) },
> +	[RESET_AUDIO]	= { CMU_DEVRST0, BIT(17) },
> +	[RESET_PCM0]	= { CMU_DEVRST0, BIT(18) },
> +	[RESET_VDE]	= { CMU_DEVRST0, BIT(19) },
> +	[RESET_VCE]	= { CMU_DEVRST0, BIT(20) },
> +	[RESET_GPU3D]	= { CMU_DEVRST0, BIT(22) },
> +	[RESET_NIC301]	= { CMU_DEVRST0, BIT(23) },
> +	[RESET_LENS]	= { CMU_DEVRST0, BIT(26) },
> +	[RESET_PERIPHRESET] = { CMU_DEVRST0, BIT(27) },
> +	[RESET_USB2_0]	= { CMU_DEVRST1, BIT(0) },
> +	[RESET_TVOUT]	= { CMU_DEVRST1, BIT(1) },
> +	[RESET_HDMI]	= { CMU_DEVRST1, BIT(2) },
> +	[RESET_HDCP2TX]	= { CMU_DEVRST1, BIT(3) },
> +	[RESET_UART6]	= { CMU_DEVRST1, BIT(4) },
> +	[RESET_UART0]	= { CMU_DEVRST1, BIT(5) },
> +	[RESET_UART1]	= { CMU_DEVRST1, BIT(6) },
> +	[RESET_UART2]	= { CMU_DEVRST1, BIT(7) },
> +	[RESET_SPI0]	= { CMU_DEVRST1, BIT(8) },
> +	[RESET_SPI1]	= { CMU_DEVRST1, BIT(9) },
> +	[RESET_SPI2]	= { CMU_DEVRST1, BIT(10) },
> +	[RESET_SPI3]	= { CMU_DEVRST1, BIT(11) },
> +	[RESET_I2C0]	= { CMU_DEVRST1, BIT(12) },
> +	[RESET_I2C1]	= { CMU_DEVRST1, BIT(13) },
> +	[RESET_USB3]	= { CMU_DEVRST1, BIT(14) },
> +	[RESET_UART3]	= { CMU_DEVRST1, BIT(15) },
> +	[RESET_UART4]	= { CMU_DEVRST1, BIT(16) },
> +	[RESET_UART5]	= { CMU_DEVRST1, BIT(17) },
> +	[RESET_I2C2]	= { CMU_DEVRST1, BIT(18) },
> +	[RESET_I2C3]	= { CMU_DEVRST1, BIT(19) },
> +	[RESET_ETHERNET] = { CMU_DEVRST1, BIT(20) },
> +	[RESET_CHIPID]	= { CMU_DEVRST1, BIT(21) },
> +	[RESET_USB2_1]	= { CMU_DEVRST1, BIT(22) },
> +	[RESET_WD0RESET] = { CMU_DEVRST1, BIT(24) },
> +	[RESET_WD1RESET] = { CMU_DEVRST1, BIT(25) },
> +	[RESET_WD2RESET] = { CMU_DEVRST1, BIT(26) },
> +	[RESET_WD3RESET] = { CMU_DEVRST1, BIT(27) },
> +	[RESET_DBG0RESET] = { CMU_DEVRST1, BIT(28) },
> +	[RESET_DBG1RESET] = { CMU_DEVRST1, BIT(29) },
> +	[RESET_DBG2RESET] = { CMU_DEVRST1, BIT(30) },
> +	[RESET_DBG3RESET] = { CMU_DEVRST1, BIT(31) },
> +};
> +
>  static struct owl_clk_desc s500_clk_desc = {
>  	.clks	    = s500_clks,
>  	.num_clks   = ARRAY_SIZE(s500_clks),
>  
>  	.hw_clks    = &s500_hw_clks,
> +
> +	.resets     = s500_resets,
> +	.num_resets = ARRAY_SIZE(s500_resets),
>  };
>  
>  static int s500_clk_probe(struct platform_device *pdev)
>  {
>  	struct owl_clk_desc *desc;
> +	struct owl_reset *reset;
> +	int ret;
>  
>  	desc = &s500_clk_desc;
>  	owl_clk_regmap_init(pdev, desc);
>  
> +	reset = devm_kzalloc(&pdev->dev, sizeof(*reset), GFP_KERNEL);
> +	if (!reset)
> +		return -ENOMEM;
> +
> +	reset->rcdev.of_node = pdev->dev.of_node;
> +	reset->rcdev.ops = &owl_reset_ops;
> +	reset->rcdev.nr_resets = desc->num_resets;
> +	reset->reset_map = desc->resets;
> +	reset->regmap = desc->regmap;
> +
> +	ret = devm_reset_controller_register(&pdev->dev, &reset->rcdev);
> +	if (ret)
> +		dev_err(&pdev->dev, "Failed to register reset controller\n");
> +
>  	return owl_clk_probe(&pdev->dev, desc->hw_clks);
>  }
>  
> -- 
> 2.27.0
>
Manivannan Sadhasivam June 26, 2020, 1:54 p.m. UTC | #3 
On Wed, Jun 24, 2020 at 08:47:57PM +0300, Cristian Ciocaltea wrote:
> Add a reset binding entry to match all members of Actions Semi Owl SoCs.
> 
> Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> ---
>  MAINTAINERS | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/MAINTAINERS b/MAINTAINERS
> index 7b5ffd646c6b..e6285c13bab0 100644
> --- a/MAINTAINERS
> +++ b/MAINTAINERS
> @@ -1533,6 +1533,7 @@ F:	drivers/mmc/host/owl-mmc.c
>  F:	drivers/pinctrl/actions/*
>  F:	drivers/soc/actions/
>  F:	include/dt-bindings/power/owl-*
> +F:	include/dt-bindings/reset/actions,*-reset.h

You can just use, reset/actions,*

Thanks,
Mani

>  F:	include/linux/soc/actions/
>  N:	owl
>  
> -- 
> 2.27.0
>
Cristian Ciocaltea June 26, 2020, 3:49 p.m. UTC | #4 
On Fri, Jun 26, 2020 at 07:15:41PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Jun 24, 2020 at 08:47:52PM +0300, Cristian Ciocaltea wrote:
> > The h_clk clock in the Actions Semi S500 SoC clock driver has an
> > invalid parent. Replace with the correct one.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> 
> Reviewed-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
> 
> You should add fixes tag for this patch and it needs to be backported as well.
> 
> Thanks,
> Mani

Right, I added the tag:

Fixes: ed6b4795ece4 ("clk: actions: Add clock driver for S500 SoC")

Thanks,
Cristi

> 
> > ---
> >  drivers/clk/actions/owl-s500.c | 2 +-
> >  1 file changed, 1 insertion(+), 1 deletion(-)
> > 
> > diff --git a/drivers/clk/actions/owl-s500.c b/drivers/clk/actions/owl-s500.c
> > index e2007ac4d235..0eb83a0b70bc 100644
> > --- a/drivers/clk/actions/owl-s500.c
> > +++ b/drivers/clk/actions/owl-s500.c
> > @@ -183,7 +183,7 @@ static OWL_GATE(timer_clk, "timer_clk", "hosc", CMU_DEVCLKEN1, 27, 0, 0);
> >  static OWL_GATE(hdmi_clk, "hdmi_clk", "hosc", CMU_DEVCLKEN1, 3, 0, 0);
> >  
> >  /* divider clocks */
> > -static OWL_DIVIDER(h_clk, "h_clk", "ahbprevdiv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> > +static OWL_DIVIDER(h_clk, "h_clk", "ahbprediv_clk", CMU_BUSCLK1, 12, 2, NULL, 0, 0);
> >  static OWL_DIVIDER(rmii_ref_clk, "rmii_ref_clk", "ethernet_pll_clk", CMU_ETHERNETPLL, 1, 1, rmii_ref_div_table, 0, 0);
> >  
> >  /* factor clocks */
> > -- 
> > 2.27.0
> >
Cristian Ciocaltea June 26, 2020, 3:58 p.m. UTC | #5 
On Fri, Jun 26, 2020 at 07:24:16PM +0530, Manivannan Sadhasivam wrote:
> On Wed, Jun 24, 2020 at 08:47:57PM +0300, Cristian Ciocaltea wrote:
> > Add a reset binding entry to match all members of Actions Semi Owl SoCs.
> > 
> > Signed-off-by: Cristian Ciocaltea <cristian.ciocaltea@gmail.com>
> > ---
> >  MAINTAINERS | 1 +
> >  1 file changed, 1 insertion(+)
> > 
> > diff --git a/MAINTAINERS b/MAINTAINERS
> > index 7b5ffd646c6b..e6285c13bab0 100644
> > --- a/MAINTAINERS
> > +++ b/MAINTAINERS
> > @@ -1533,6 +1533,7 @@ F:	drivers/mmc/host/owl-mmc.c
> >  F:	drivers/pinctrl/actions/*
> >  F:	drivers/soc/actions/
> >  F:	include/dt-bindings/power/owl-*
> > +F:	include/dt-bindings/reset/actions,*-reset.h
> 
> You can just use, reset/actions,*
> 
> Thanks,
> Mani

Done, thanks!

> 
> >  F:	include/linux/soc/actions/
> >  N:	owl
> >  
> > -- 
> > 2.27.0
> >