| Message ID | 1585128694-13881-2-git-send-email-hanks.chen@mediatek.com |
|---|---|
| State | Changes Requested, archived |
| Headers | show |
| Series | Add basic SoC Support for Mediatek MT6779 SoC | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | fail | build log |
On Wed, 25 Mar 2020 17:31:29 +0800, Hanks Chen wrote: > From: Andy Teng <andy.teng@mediatek.com> > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > Signed-off-by: Andy Teng <andy.teng@mediatek.com> > --- > .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 208 ++++++++++++++++++++ > 1 file changed, 208 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > My bot found errors running 'make dt_binding_check' on your patch: Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dts:19:18: fatal error: dt-bindings/pinctrl/mt6779-pinfunc.h: No such file or directory #include <dt-bindings/pinctrl/mt6779-pinfunc.h> ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ compilation terminated. scripts/Makefile.lib:311: recipe for target 'Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml' failed make[1]: *** [Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.example.dt.yaml] Error 1 make[1]: *** Waiting for unfinished jobs.... Makefile:1262: recipe for target 'dt_binding_check' failed make: *** [dt_binding_check] Error 2 See https://patchwork.ozlabs.org/patch/1261248 If you already ran 'make dt_binding_check' and didn't see the above error(s), then make sure dt-schema is up to date: pip3 install git+https://github.com/devicetree-org/dt-schema.git@master --upgrade Please check and re-submit.
On Wed, Mar 25, 2020 at 3:31 AM Hanks Chen <hanks.chen@mediatek.com> wrote: > > From: Andy Teng <andy.teng@mediatek.com> > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > Signed-off-by: Andy Teng <andy.teng@mediatek.com> > --- > .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 208 ++++++++++++++++++++ > 1 file changed, 208 insertions(+) > create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml The header belongs in this patch so that 'make dt_binding_check' works. > > diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > new file mode 100644 > index 0000000..5f9bbf1 > --- /dev/null > +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > @@ -0,0 +1,208 @@ > +# SPDX-License-Identifier: GPL-2.0 > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Mediatek MT6779 Pin Controller Device Tree Bindings > + > +maintainers: > + - Andy Teng <andy.teng@mediatek.com> > + > +description: |+ > + The pin controller node should be the child of a syscon node with the > + required property: > + - compatible: "syscon" > + > +properties: > + compatible: > + const: mediatek,mt6779-pinctrl > + > + reg: > + minItems: 9 > + maxItems: 9 > + description: | > + physical address base for gpio-related control registers. > + > + reg-names: > + description: | > + GPIO base register names. Need to define what the names are and the order. > + > + gpio-controller: true > + > + "#gpio-cells": > + const: 2 > + description: | > + Number of cells in GPIO specifier. Since the generic GPIO > + binding is used, the amount of cells must be specified as 2. See the below > + mentioned gpio binding representation for description of particular cells. > + > + gpio-ranges: > + minItems: 1 > + maxItems: 5 > + description: | > + GPIO valid number range. > + > + interrupt-controller: true > + > + interrupts: > + minItems: 1 > + maxItems: 4 Need to define what the interrupts are. > + description: | > + The interrupt outputs to sysirq. > + > + "#interrupt-cells": > + const: 2 > + > +required: > + - compatible > + - reg > + - reg-names > + - gpio-controller > + - "#gpio-cells" > + - gpio-ranges > + - interrupt-controller > + - interrupts > + - "#interrupt-cells" > + > +patternProperties: > + '^pins*$': '-pins$' would be preferred. > + type: object > + description: | > + A pinctrl node should contain at least one subnodes representing the > + pinctrl groups available on the machine. Each subnode will list the > + pins it needs, and how they should be configured, with regard to muxer > + configuration, pullups, drive strength, input enable/disable and input schmitt. > + > + properties: > + pinmux: There's a common schema for all these properties. You need to reference it (with $ref) and only define which properties you are using and any additional constraints. > + description: > + integer array, represents gpio pin number and mux setting. > + Supported pin number and mux varies for different SoCs, and are defined > + as macros in boot/dts/<soc>-pinfunc.h directly. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32-array > + bias-disable: > + type: boolean > + > + bias-pull-up: > + oneOf: > + - type: boolean > + - $ref: /schemas/types.yaml#/definitions/uint32 > + > + bias-pull-down: > + oneOf: > + - type: boolean > + - $ref: /schemas/types.yaml#/definitions/uint32 > + > + input-enable: > + type: boolean > + > + input-disable: > + type: boolean > + > + output-low: > + type: boolean > + > + output-high: > + type: boolean > + > + input-schmitt-enable: > + type: boolean > + > + input-schmitt-disable: > + type: boolean > + > + mediatek,pull-up-adv: > + description: | > + Pull up setings for 2 pull resistors, R0 and R1. User can > + configure those special pins. Valid arguments are described as below: > + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. > + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. > + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. > + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - enum: [0, 1, 2, 3] > + > + mediatek,pull-down-adv: > + description: | > + Pull down settings for 2 pull resistors, R0 and R1. User can > + configure those special pins. Valid arguments are described as below: > + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. > + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. > + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. > + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - enum: [0, 1, 2, 3] > + > + drive-strength: > + description: | > + Selects the drive strength for the specified pins in mA. > + allOf: > + - $ref: /schemas/types.yaml#/definitions/uint32 > + - enum: [2, 4, 6, 8, 10, 12, 14, 16] > + > + required: > + - pinmux Add: additionalProperties: false additionalProperties: false > + > +examples: > + - | > + #include <dt-bindings/interrupt-controller/irq.h> > + #include <dt-bindings/interrupt-controller/arm-gic.h> > + #include <dt-bindings/pinctrl/mt6779-pinfunc.h> > + > + pio: pinctrl@10005000 { > + compatible = "mediatek,mt6779-pinctrl"; > + reg = <0 0x10005000 0 0x1000>, > + <0 0x11c20000 0 0x1000>, > + <0 0x11d10000 0 0x1000>, > + <0 0x11e20000 0 0x1000>, > + <0 0x11e70000 0 0x1000>, > + <0 0x11ea0000 0 0x1000>, > + <0 0x11f20000 0 0x1000>, > + <0 0x11f30000 0 0x1000>, > + <0 0x1000b000 0 0x1000>; > + reg-names = "gpio", "iocfg_rm", > + "iocfg_br", "iocfg_lm", > + "iocfg_lb", "iocfg_rt", > + "iocfg_lt", "iocfg_tl", > + "eint"; > + gpio-controller; > + #gpio-cells = <2>; > + gpio-ranges = <&pio 0 0 210>; > + interrupt-controller; > + #interrupt-cells = <2>; > + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; > + > + mmc0_pins_default: mmc0default { > + pins_cmd_dat { The 2 levels of nodes here doesn't match your schema. Also, don't use '_' in node names. > + pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>, > + <PINMUX_GPIO172__FUNC_MSDC0_DAT1>, > + <PINMUX_GPIO169__FUNC_MSDC0_DAT2>, > + <PINMUX_GPIO177__FUNC_MSDC0_DAT3>, > + <PINMUX_GPIO170__FUNC_MSDC0_DAT4>, > + <PINMUX_GPIO173__FUNC_MSDC0_DAT5>, > + <PINMUX_GPIO171__FUNC_MSDC0_DAT6>, > + <PINMUX_GPIO174__FUNC_MSDC0_DAT7>, > + <PINMUX_GPIO167__FUNC_MSDC0_CMD>; > + input-enable; > + mediatek,pull-up-adv = <1>; > + }; > + pins_clk { > + pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>; > + mediatek,pull-down-adv = <2>; > + }; > + pins_rst { > + pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>; > + mediatek,pull-up-adv = <0>; > + }; > + }; > + > + mmc0 { > + pinctrl-0 = <&mmc0_pins_default>; > + pinctrl-names = "default"; > + }; > + }; > + > -- > 1.7.9.5
On Thu, 2020-03-26 at 11:43 -0600, Rob Herring wrote: > On Wed, Mar 25, 2020 at 3:31 AM Hanks Chen <hanks.chen@mediatek.com> wrote: > > > > From: Andy Teng <andy.teng@mediatek.com> > > > > Add devicetree bindings for MediaTek MT6779 pinctrl driver. > > > > Signed-off-by: Andy Teng <andy.teng@mediatek.com> > > --- > > .../bindings/pinctrl/mediatek,mt6779-pinctrl.yaml | 208 ++++++++++++++++++++ > > 1 file changed, 208 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > The header belongs in this patch so that 'make dt_binding_check' works. > > > > > diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > new file mode 100644 > > index 0000000..5f9bbf1 > > --- /dev/null > > +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml > > @@ -0,0 +1,208 @@ > > +# SPDX-License-Identifier: GPL-2.0 > > +%YAML 1.2 > > +--- > > +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# > > +$schema: http://devicetree.org/meta-schemas/core.yaml# > > + > > +title: Mediatek MT6779 Pin Controller Device Tree Bindings > > + > > +maintainers: > > + - Andy Teng <andy.teng@mediatek.com> > > + > > +description: |+ > > + The pin controller node should be the child of a syscon node with the > > + required property: > > + - compatible: "syscon" > > + > > +properties: > > + compatible: > > + const: mediatek,mt6779-pinctrl > > + > > + reg: > > + minItems: 9 > > + maxItems: 9 > > + description: | > > + physical address base for gpio-related control registers. > > + > > + reg-names: > > + description: | > > + GPIO base register names. > > Need to define what the names are and the order. Got it, I'll add it in next version. Thanks > > > + > > + gpio-controller: true > > + > > + "#gpio-cells": > > + const: 2 > > + description: | > > + Number of cells in GPIO specifier. Since the generic GPIO > > + binding is used, the amount of cells must be specified as 2. See the below > > + mentioned gpio binding representation for description of particular cells. > > + > > + gpio-ranges: > > + minItems: 1 > > + maxItems: 5 > > + description: | > > + GPIO valid number range. > > + > > + interrupt-controller: true > > + > > + interrupts: > > + minItems: 1 > > + maxItems: 4 > > Need to define what the interrupts are. > Got it, I'll add it in the next version. Thanks. > > + description: | > > + The interrupt outputs to sysirq. > > + > > + "#interrupt-cells": > > + const: 2 > > + > > +required: > > + - compatible > > + - reg > > + - reg-names > > + - gpio-controller > > + - "#gpio-cells" > > + - gpio-ranges > > + - interrupt-controller > > + - interrupts > > + - "#interrupt-cells" > > + > > +patternProperties: > > + '^pins*$': > > '-pins$' would be preferred. > Got it, I'll fix it in next version. Thanks. > > + type: object > > + description: | > > + A pinctrl node should contain at least one subnodes representing the > > + pinctrl groups available on the machine. Each subnode will list the > > + pins it needs, and how they should be configured, with regard to muxer > > + configuration, pullups, drive strength, input enable/disable and input schmitt. > > + > > + properties: > > + pinmux: > > There's a common schema for all these properties. You need to > reference it (with $ref) and only define which properties you are > using and any additional constraints. > Got it, thx! > > + description: > > + integer array, represents gpio pin number and mux setting. > > + Supported pin number and mux varies for different SoCs, and are defined > > + as macros in boot/dts/<soc>-pinfunc.h directly. > > + allOf: > > + - $ref: /schemas/types.yaml#/definitions/uint32-array > > + bias-disable: > > + type: boolean > > + > > + bias-pull-up: > > + oneOf: > > + - type: boolean > > + - $ref: /schemas/types.yaml#/definitions/uint32 > > + > > + bias-pull-down: > > + oneOf: > > + - type: boolean > > + - $ref: /schemas/types.yaml#/definitions/uint32 > > + > > + input-enable: > > + type: boolean > > + > > + input-disable: > > + type: boolean > > + > > + output-low: > > + type: boolean > > + > > + output-high: > > + type: boolean > > + > > + input-schmitt-enable: > > + type: boolean > > + > > + input-schmitt-disable: > > + type: boolean > > + > > + mediatek,pull-up-adv: > > + description: | > > + Pull up setings for 2 pull resistors, R0 and R1. User can > > + configure those special pins. Valid arguments are described as below: > > + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. > > + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. > > + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. > > + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. > > + allOf: > > + - $ref: /schemas/types.yaml#/definitions/uint32 > > + - enum: [0, 1, 2, 3] > > + > > + mediatek,pull-down-adv: > > + description: | > > + Pull down settings for 2 pull resistors, R0 and R1. User can > > + configure those special pins. Valid arguments are described as below: > > + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. > > + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. > > + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. > > + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. > > + allOf: > > + - $ref: /schemas/types.yaml#/definitions/uint32 > > + - enum: [0, 1, 2, 3] > > + > > + drive-strength: > > + description: | > > + Selects the drive strength for the specified pins in mA. > > + allOf: > > + - $ref: /schemas/types.yaml#/definitions/uint32 > > + - enum: [2, 4, 6, 8, 10, 12, 14, 16] > > + > > + required: > > + - pinmux > > Add: > > additionalProperties: false > > additionalProperties: false > Got it, I'll add it, thx! > > + > > +examples: > > + - | > > + #include <dt-bindings/interrupt-controller/irq.h> > > + #include <dt-bindings/interrupt-controller/arm-gic.h> > > + #include <dt-bindings/pinctrl/mt6779-pinfunc.h> > > + > > + pio: pinctrl@10005000 { > > + compatible = "mediatek,mt6779-pinctrl"; > > + reg = <0 0x10005000 0 0x1000>, > > + <0 0x11c20000 0 0x1000>, > > + <0 0x11d10000 0 0x1000>, > > + <0 0x11e20000 0 0x1000>, > > + <0 0x11e70000 0 0x1000>, > > + <0 0x11ea0000 0 0x1000>, > > + <0 0x11f20000 0 0x1000>, > > + <0 0x11f30000 0 0x1000>, > > + <0 0x1000b000 0 0x1000>; > > + reg-names = "gpio", "iocfg_rm", > > + "iocfg_br", "iocfg_lm", > > + "iocfg_lb", "iocfg_rt", > > + "iocfg_lt", "iocfg_tl", > > + "eint"; > > + gpio-controller; > > + #gpio-cells = <2>; > > + gpio-ranges = <&pio 0 0 210>; > > + interrupt-controller; > > + #interrupt-cells = <2>; > > + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; > > + > > + mmc0_pins_default: mmc0default { > > + pins_cmd_dat { > > The 2 levels of nodes here doesn't match your schema. > > Also, don't use '_' in node names. > I'll fix it in next version, thx! > > + pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>, > > + <PINMUX_GPIO172__FUNC_MSDC0_DAT1>, > > + <PINMUX_GPIO169__FUNC_MSDC0_DAT2>, > > + <PINMUX_GPIO177__FUNC_MSDC0_DAT3>, > > + <PINMUX_GPIO170__FUNC_MSDC0_DAT4>, > > + <PINMUX_GPIO173__FUNC_MSDC0_DAT5>, > > + <PINMUX_GPIO171__FUNC_MSDC0_DAT6>, > > + <PINMUX_GPIO174__FUNC_MSDC0_DAT7>, > > + <PINMUX_GPIO167__FUNC_MSDC0_CMD>; > > + input-enable; > > + mediatek,pull-up-adv = <1>; > > + }; > > + pins_clk { > > + pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>; > > + mediatek,pull-down-adv = <2>; > > + }; > > + pins_rst { > > + pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>; > > + mediatek,pull-up-adv = <0>; > > + }; > > + }; > > + > > + mmc0 { > > + pinctrl-0 = <&mmc0_pins_default>; > > + pinctrl-names = "default"; > > + }; > > + }; > > + > > -- > > 1.7.9.5
diff --git a/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml new file mode 100644 index 0000000..5f9bbf1 --- /dev/null +++ b/Documentation/devicetree/bindings/pinctrl/mediatek,mt6779-pinctrl.yaml @@ -0,0 +1,208 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/pinctrl/mediatek,mt6779-pinctrl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Mediatek MT6779 Pin Controller Device Tree Bindings + +maintainers: + - Andy Teng <andy.teng@mediatek.com> + +description: |+ + The pin controller node should be the child of a syscon node with the + required property: + - compatible: "syscon" + +properties: + compatible: + const: mediatek,mt6779-pinctrl + + reg: + minItems: 9 + maxItems: 9 + description: | + physical address base for gpio-related control registers. + + reg-names: + description: | + GPIO base register names. + + gpio-controller: true + + "#gpio-cells": + const: 2 + description: | + Number of cells in GPIO specifier. Since the generic GPIO + binding is used, the amount of cells must be specified as 2. See the below + mentioned gpio binding representation for description of particular cells. + + gpio-ranges: + minItems: 1 + maxItems: 5 + description: | + GPIO valid number range. + + interrupt-controller: true + + interrupts: + minItems: 1 + maxItems: 4 + description: | + The interrupt outputs to sysirq. + + "#interrupt-cells": + const: 2 + +required: + - compatible + - reg + - reg-names + - gpio-controller + - "#gpio-cells" + - gpio-ranges + - interrupt-controller + - interrupts + - "#interrupt-cells" + +patternProperties: + '^pins*$': + type: object + description: | + A pinctrl node should contain at least one subnodes representing the + pinctrl groups available on the machine. Each subnode will list the + pins it needs, and how they should be configured, with regard to muxer + configuration, pullups, drive strength, input enable/disable and input schmitt. + + properties: + pinmux: + description: + integer array, represents gpio pin number and mux setting. + Supported pin number and mux varies for different SoCs, and are defined + as macros in boot/dts/<soc>-pinfunc.h directly. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32-array + bias-disable: + type: boolean + + bias-pull-up: + oneOf: + - type: boolean + - $ref: /schemas/types.yaml#/definitions/uint32 + + bias-pull-down: + oneOf: + - type: boolean + - $ref: /schemas/types.yaml#/definitions/uint32 + + input-enable: + type: boolean + + input-disable: + type: boolean + + output-low: + type: boolean + + output-high: + type: boolean + + input-schmitt-enable: + type: boolean + + input-schmitt-disable: + type: boolean + + mediatek,pull-up-adv: + description: | + Pull up setings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3] + + mediatek,pull-down-adv: + description: | + Pull down settings for 2 pull resistors, R0 and R1. User can + configure those special pins. Valid arguments are described as below: + 0: (R1, R0) = (0, 0) which means R1 disabled and R0 disable. + 1: (R1, R0) = (0, 1) which means R1 disabled and R0 enabled. + 2: (R1, R0) = (1, 0) which means R1 enabled and R0 disabled. + 3: (R1, R0) = (1, 1) which means R1 enabled and R0 enabled. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3] + + drive-strength: + description: | + Selects the drive strength for the specified pins in mA. + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [2, 4, 6, 8, 10, 12, 14, 16] + + required: + - pinmux + +examples: + - | + #include <dt-bindings/interrupt-controller/irq.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/pinctrl/mt6779-pinfunc.h> + + pio: pinctrl@10005000 { + compatible = "mediatek,mt6779-pinctrl"; + reg = <0 0x10005000 0 0x1000>, + <0 0x11c20000 0 0x1000>, + <0 0x11d10000 0 0x1000>, + <0 0x11e20000 0 0x1000>, + <0 0x11e70000 0 0x1000>, + <0 0x11ea0000 0 0x1000>, + <0 0x11f20000 0 0x1000>, + <0 0x11f30000 0 0x1000>, + <0 0x1000b000 0 0x1000>; + reg-names = "gpio", "iocfg_rm", + "iocfg_br", "iocfg_lm", + "iocfg_lb", "iocfg_rt", + "iocfg_lt", "iocfg_tl", + "eint"; + gpio-controller; + #gpio-cells = <2>; + gpio-ranges = <&pio 0 0 210>; + interrupt-controller; + #interrupt-cells = <2>; + interrupts = <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>; + + mmc0_pins_default: mmc0default { + pins_cmd_dat { + pinmux = <PINMUX_GPIO168__FUNC_MSDC0_DAT0>, + <PINMUX_GPIO172__FUNC_MSDC0_DAT1>, + <PINMUX_GPIO169__FUNC_MSDC0_DAT2>, + <PINMUX_GPIO177__FUNC_MSDC0_DAT3>, + <PINMUX_GPIO170__FUNC_MSDC0_DAT4>, + <PINMUX_GPIO173__FUNC_MSDC0_DAT5>, + <PINMUX_GPIO171__FUNC_MSDC0_DAT6>, + <PINMUX_GPIO174__FUNC_MSDC0_DAT7>, + <PINMUX_GPIO167__FUNC_MSDC0_CMD>; + input-enable; + mediatek,pull-up-adv = <1>; + }; + pins_clk { + pinmux = <PINMUX_GPIO176__FUNC_MSDC0_CLK>; + mediatek,pull-down-adv = <2>; + }; + pins_rst { + pinmux = <PINMUX_GPIO178__FUNC_MSDC0_RSTB>; + mediatek,pull-up-adv = <0>; + }; + }; + + mmc0 { + pinctrl-0 = <&mmc0_pins_default>; + pinctrl-names = "default"; + }; + }; +