| Message ID | 20200526125928.17096-4-Sergey.Semin@baikalelectronics.ru |
|---|---|
| State | Not Applicable, archived |
| Headers | show |
| Series | bus/memory: Add Baikal-T1 SoC APB/AXI/L2 drivers | expand |
| Context | Check | Description |
|---|---|---|
| robh/checkpatch | success | |
| robh/dt-meta-schema | fail | build log |
On Tue, 26 May 2020 15:59:25 +0300, Serge Semin wrote: > There is a single register provided by the SoC system controller, > which can be used to tune the L2-cache RAM up. It only provides a way > to change the L2-RAM access latencies. So aside from "be,bt1-l2-ctl" > compatible string the device node can be optionally equipped with the > properties of Tag/Data/WS latencies. > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> > Cc: Paul Burton <paulburton@kernel.org> > Cc: Olof Johansson <olof@lixom.net> > Cc: linux-mips@vger.kernel.org > Cc: soc@kernel.org > > --- > > Changelog v2: > - Move driver to the memory subsystem. > - Use dual GPL/BSD license. > - Use single lined copyright header. > - Move "allOf" restrictions to the root level of the properties. > - Discard syscon compatible string and reg property. > - The DT node is supposed to be a child of the Baikal-T1 system controller > node. > > Changelog v3: > - Get the reg property back even though the driver is using the parental > syscon regmap. > - The DT schema will live separately from the system controller, but the > corresponding sub-node of the later DT schema will $ref this one. > - Set non-default latencies in the example. > --- > .../memory-controllers/baikal,bt1-l2-ctl.yaml | 63 +++++++++++++++++++ > 1 file changed, 63 insertions(+) > create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml > Reviewed-by: Rob Herring <robh@kernel.org>
On Tue, May 26, 2020 at 10:09:15AM -0600, Rob Herring wrote: > On Tue, 26 May 2020 15:59:25 +0300, Serge Semin wrote: > > There is a single register provided by the SoC system controller, > > which can be used to tune the L2-cache RAM up. It only provides a way > > to change the L2-RAM access latencies. So aside from "be,bt1-l2-ctl" > > compatible string the device node can be optionally equipped with the > > properties of Tag/Data/WS latencies. > > > > Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> > > Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> > > Cc: Paul Burton <paulburton@kernel.org> > > Cc: Olof Johansson <olof@lixom.net> > > Cc: linux-mips@vger.kernel.org > > Cc: soc@kernel.org > > > > --- > > > > Changelog v2: > > - Move driver to the memory subsystem. > > - Use dual GPL/BSD license. > > - Use single lined copyright header. > > - Move "allOf" restrictions to the root level of the properties. > > - Discard syscon compatible string and reg property. > > - The DT node is supposed to be a child of the Baikal-T1 system controller > > node. > > > > Changelog v3: > > - Get the reg property back even though the driver is using the parental > > syscon regmap. > > - The DT schema will live separately from the system controller, but the > > corresponding sub-node of the later DT schema will $ref this one. > > - Set non-default latencies in the example. > > --- > > .../memory-controllers/baikal,bt1-l2-ctl.yaml | 63 +++++++++++++++++++ > > 1 file changed, 63 insertions(+) > > create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml > > > > Reviewed-by: Rob Herring <robh@kernel.org> Great! Thanks. -Sergey
diff --git a/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml new file mode 100644 index 000000000000..1fca282f64a2 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml @@ -0,0 +1,63 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +# Copyright (C) 2020 BAIKAL ELECTRONICS, JSC +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/baikal,bt1-l2-ctl.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Baikal-T1 L2-cache Control Block + +maintainers: + - Serge Semin <fancer.lancer@gmail.com> + +description: | + By means of the System Controller Baikal-T1 SoC exposes a few settings to + tune the MIPS P5600 CM2 L2 cache performance up. In particular it's possible + to change the Tag, Data and Way-select RAM access latencies. Baikal-T1 + L2-cache controller block is responsible for the tuning. Its DT node is + supposed to be a child of the system controller. + +properties: + compatible: + const: baikal,bt1-l2-ctl + + reg: + maxItems: 1 + + baikal,l2-ws-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Way-select RAM accesses + default: 0 + minimum: 0 + maximum: 3 + + baikal,l2-tag-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Tag RAM accesses + default: 0 + minimum: 0 + maximum: 3 + + baikal,l2-data-latency: + $ref: /schemas/types.yaml#/definitions/uint32 + description: Cycles of latency for Data RAM accesses + default: 1 + minimum: 0 + maximum: 3 + +additionalProperties: false + +required: + - compatible + +examples: + - | + l2@1f04d028 { + compatible = "baikal,bt1-l2-ctl"; + reg = <0x1f04d028 0x004>; + + baikal,l2-ws-latency = <1>; + baikal,l2-tag-latency = <1>; + baikal,l2-data-latency = <2>; + }; +...
There is a single register provided by the SoC system controller, which can be used to tune the L2-cache RAM up. It only provides a way to change the L2-RAM access latencies. So aside from "be,bt1-l2-ctl" compatible string the device node can be optionally equipped with the properties of Tag/Data/WS latencies. Signed-off-by: Serge Semin <Sergey.Semin@baikalelectronics.ru> Cc: Alexey Malahov <Alexey.Malahov@baikalelectronics.ru> Cc: Paul Burton <paulburton@kernel.org> Cc: Olof Johansson <olof@lixom.net> Cc: linux-mips@vger.kernel.org Cc: soc@kernel.org --- Changelog v2: - Move driver to the memory subsystem. - Use dual GPL/BSD license. - Use single lined copyright header. - Move "allOf" restrictions to the root level of the properties. - Discard syscon compatible string and reg property. - The DT node is supposed to be a child of the Baikal-T1 system controller node. Changelog v3: - Get the reg property back even though the driver is using the parental syscon regmap. - The DT schema will live separately from the system controller, but the corresponding sub-node of the later DT schema will $ref this one. - Set non-default latencies in the example. --- .../memory-controllers/baikal,bt1-l2-ctl.yaml | 63 +++++++++++++++++++ 1 file changed, 63 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/baikal,bt1-l2-ctl.yaml