| Message ID | 20200513062617.19988-12-pragnesh.patel@sifive.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | RISC-V SiFive FU540 support SPL | expand |
On Wed, May 13, 2020 at 11:57 AM Pragnesh Patel <pragnesh.patel@sifive.com> wrote: > > Release ethernet clock reset Please add a detailed commit message of why the ethernet clock is resetting in SPL code since ethernet won't need for SPL at all? Jagan.
Hi Jagan, >-----Original Message----- >From: Jagan Teki <jagan@amarulasolutions.com> >Sent: 13 May 2020 12:21 >To: Pragnesh Patel <pragnesh.patel@sifive.com> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra ><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; Bin >Meng <bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>; >Anup Patel <anup.patel@wdc.com>; Sagar Kadam ><sagar.kadam@sifive.com>; Rick Chen <rick@andestech.com>; Lukasz >Majewski <lukma@denx.de>; Anatolij Gustschin <agust@denx.de>; Simon >Glass <sjg@chromium.org> >Subject: Re: [PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock >reset > >[External Email] Do not click links or attachments unless you recognize the >sender and know the content is safe > >On Wed, May 13, 2020 at 11:57 AM Pragnesh Patel ><pragnesh.patel@sifive.com> wrote: >> >> Release ethernet clock reset > >Please add a detailed commit message of why the ethernet clock is resetting in >SPL code since ethernet won't need for SPL at all? Once the ethernet clock has been initialized ( set_rate() and clk_enable() ), we need to take ethernet clock out of reset. This patch is necessary in this series otherwise U-Boot cannot use ethernet and not able To boot. This ethernet reset __prci_ethernet_release_reset() is not depend on SPL or U-Boot proper. Right now, U-Boot proper is using ethernet so this gets called only for U-Boot proper and if SPL wants to use ethernet then function helps to take clock out of reset. I will update the commit description in v10. > >Jagan.
On Wed, May 13, 2020 at 12:48 PM Pragnesh Patel <pragnesh.patel@sifive.com> wrote: > > Hi Jagan, > > >-----Original Message----- > >From: Jagan Teki <jagan@amarulasolutions.com> > >Sent: 13 May 2020 12:21 > >To: Pragnesh Patel <pragnesh.patel@sifive.com> > >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra > ><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; Bin > >Meng <bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>; > >Anup Patel <anup.patel@wdc.com>; Sagar Kadam > ><sagar.kadam@sifive.com>; Rick Chen <rick@andestech.com>; Lukasz > >Majewski <lukma@denx.de>; Anatolij Gustschin <agust@denx.de>; Simon > >Glass <sjg@chromium.org> > >Subject: Re: [PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock > >reset > > > >[External Email] Do not click links or attachments unless you recognize the > >sender and know the content is safe > > > >On Wed, May 13, 2020 at 11:57 AM Pragnesh Patel > ><pragnesh.patel@sifive.com> wrote: > >> > >> Release ethernet clock reset > > > >Please add a detailed commit message of why the ethernet clock is resetting in > >SPL code since ethernet won't need for SPL at all? > > Once the ethernet clock has been initialized ( set_rate() and clk_enable() ), we need to take > ethernet clock out of reset. > > This patch is necessary in this series otherwise U-Boot cannot use ethernet and not able > To boot. > > This ethernet reset __prci_ethernet_release_reset() is not depend on SPL or U-Boot proper. > Right now, U-Boot proper is using ethernet so this gets called only for U-Boot proper and if SPL wants > to use ethernet then function helps to take clock out of reset. But will __prci_ethernet_release_reset is called in SPL?
>-----Original Message----- >From: Jagan Teki <jagan@amarulasolutions.com> >Sent: 13 May 2020 13:30 >To: Pragnesh Patel <pragnesh.patel@sifive.com> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra ><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; Bin >Meng <bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>; >Anup Patel <anup.patel@wdc.com>; Sagar Kadam ><sagar.kadam@sifive.com>; Rick Chen <rick@andestech.com>; Lukasz >Majewski <lukma@denx.de>; Anatolij Gustschin <agust@denx.de>; Simon >Glass <sjg@chromium.org> >Subject: Re: [PATCH v9 11/18] clk: sifive: fu540-prci: release ethernet clock >reset > >[External Email] Do not click links or attachments unless you recognize the >sender and know the content is safe > >On Wed, May 13, 2020 at 12:48 PM Pragnesh Patel ><pragnesh.patel@sifive.com> wrote: >> >> Hi Jagan, >> >> >-----Original Message----- >> >From: Jagan Teki <jagan@amarulasolutions.com> >> >Sent: 13 May 2020 12:21 >> >To: Pragnesh Patel <pragnesh.patel@sifive.com> >> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra >> ><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; >Bin >> >Meng <bmeng.cn@gmail.com>; Paul Walmsley ><paul.walmsley@sifive.com>; >> >Anup Patel <anup.patel@wdc.com>; Sagar Kadam >> ><sagar.kadam@sifive.com>; Rick Chen <rick@andestech.com>; Lukasz >> >Majewski <lukma@denx.de>; Anatolij Gustschin <agust@denx.de>; Simon >> >Glass <sjg@chromium.org> >> >Subject: Re: [PATCH v9 11/18] clk: sifive: fu540-prci: release >> >ethernet clock reset >> > >> >[External Email] Do not click links or attachments unless you >> >recognize the sender and know the content is safe >> > >> >On Wed, May 13, 2020 at 11:57 AM Pragnesh Patel >> ><pragnesh.patel@sifive.com> wrote: >> >> >> >> Release ethernet clock reset >> > >> >Please add a detailed commit message of why the ethernet clock is >> >resetting in SPL code since ethernet won't need for SPL at all? >> >> Once the ethernet clock has been initialized ( set_rate() and >> clk_enable() ), we need to take ethernet clock out of reset. >> >> This patch is necessary in this series otherwise U-Boot cannot use >> ethernet and not able To boot. >> >> This ethernet reset __prci_ethernet_release_reset() is not depend on SPL or >U-Boot proper. >> Right now, U-Boot proper is using ethernet so this gets called only >> for U-Boot proper and if SPL wants to use ethernet then function helps to >take clock out of reset. > >But will __prci_ethernet_release_reset is called in SPL? Right now no but if SPL wants to use ethernet in future then this function gets called.
diff --git a/drivers/clk/sifive/fu540-prci.c b/drivers/clk/sifive/fu540-prci.c index f26a370a64..45491a77d5 100644 --- a/drivers/clk/sifive/fu540-prci.c +++ b/drivers/clk/sifive/fu540-prci.c @@ -559,6 +559,25 @@ static void __prci_ddr_release_reset(struct __prci_data *pd) asm volatile ("nop"); } +/** + * __prci_ethernet_release_reset() - Release ethernet reset + * @pd: struct __prci_data * for the PRCI containing the Ethernet CLK mux reg + * + */ +static void __prci_ethernet_release_reset(struct __prci_data *pd) +{ + u32 v; + + /* Release GEMGXL reset */ + v = __prci_readl(pd, PRCI_DEVICESRESETREG_OFFSET); + v |= PRCI_DEVICESRESETREG_GEMGXL_RST_N_MASK; + __prci_writel(v, PRCI_DEVICESRESETREG_OFFSET, pd); + + /* Procmon => core clock */ + __prci_writel(PRCI_PROCMONCFG_CORE_CLOCK_MASK, PRCI_PROCMONCFG_OFFSET, + pd); +} + /* * PRCI integration data for each WRPLL instance */ @@ -579,6 +598,7 @@ static struct __prci_wrpll_data __prci_ddrpll_data = { static struct __prci_wrpll_data __prci_gemgxlpll_data = { .cfg0_offs = PRCI_GEMGXLPLLCFG0_OFFSET, .cfg1_offs = PRCI_GEMGXLPLLCFG1_OFFSET, + .release_reset = __prci_ethernet_release_reset, }; /*
Release ethernet clock reset Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> --- drivers/clk/sifive/fu540-prci.c | 20 ++++++++++++++++++++ 1 file changed, 20 insertions(+)