| Message ID | 20200509143037.26009-20-pragnesh.patel@sifive.com |
|---|---|
| State | Superseded |
| Delegated to: | Andes |
| Headers | show |
| Series | RISC-V SiFive FU540 support SPL | expand |
On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel@sifive.com> wrote: > > Add L2 cache node to enable cache ways from U-Boot > > Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> > Reviewed-by: Bin Meng <bmeng.cn@gmail.com> > --- > arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi > index fc91a7c987..42e43522ed 100644 > --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi > +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi > @@ -82,3 +82,7 @@ > &qspi2 { > u-boot,dm-spl; > }; > + > +&l2cache { > + status = "okay"; > +}; Squash with next commit.
>-----Original Message----- >From: Jagan Teki <jagan@amarulasolutions.com> >Sent: 10 May 2020 20:44 >To: Pragnesh Patel <pragnesh.patel@sifive.com> >Cc: U-Boot-Denx <u-boot@lists.denx.de>; Atish Patra ><atish.patra@wdc.com>; Palmer Dabbelt <palmerdabbelt@google.com>; Bin >Meng <bmeng.cn@gmail.com>; Paul Walmsley <paul.walmsley@sifive.com>; >Troy Benjegerdes <troy.benjegerdes@sifive.com>; Anup Patel ><anup.patel@wdc.com>; Sagar Kadam <sagar.kadam@sifive.com>; Rick Chen ><rick@andestech.com> >Subject: Re: [PATCH v8 19/21] sifive: dts: fu540: Enable L2 Cache in U-Boot > >[External Email] Do not click links or attachments unless you recognize the >sender and know the content is safe > >On Sat, May 9, 2020 at 8:02 PM Pragnesh Patel <pragnesh.patel@sifive.com> >wrote: >> >> Add L2 cache node to enable cache ways from U-Boot >> >> Signed-off-by: Pragnesh Patel <pragnesh.patel@sifive.com> >> Reviewed-by: Bin Meng <bmeng.cn@gmail.com> >> --- >> arch/riscv/dts/fu540-c000-u-boot.dtsi | 4 ++++ >> 1 file changed, 4 insertions(+) >> >> diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540- >c000-u-boot.dtsi >> index fc91a7c987..42e43522ed 100644 >> --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi >> +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi >> @@ -82,3 +82,7 @@ >> &qspi2 { >> u-boot,dm-spl; >> }; >> + >> +&l2cache { >> + status = "okay"; >> +}; > >Squash with next commit. Will update in v9.
diff --git a/arch/riscv/dts/fu540-c000-u-boot.dtsi b/arch/riscv/dts/fu540-c000-u-boot.dtsi index fc91a7c987..42e43522ed 100644 --- a/arch/riscv/dts/fu540-c000-u-boot.dtsi +++ b/arch/riscv/dts/fu540-c000-u-boot.dtsi @@ -82,3 +82,7 @@ &qspi2 { u-boot,dm-spl; }; + +&l2cache { + status = "okay"; +};