| Message ID | 1584093227-1292-1-git-send-email-yangyicong@hisilicon.com |
|---|---|
| State | New |
| Headers | show |
| Series | [v2] PCI/ASPM: Fix wrong field set when config L1SS | expand |
On Fri, Mar 13, 2020 at 05:53:47PM +0800, Yicong Yang wrote: > We enable proper L1 substates in the end of pcie_config_aspm_l1ss(). It's > PCI_L1SS_CTL1_L1SS_MASK field should we set in PCI_L1SS_CTL1 register > rather than PCI_L1SS_CAP_L1_PM_SS. > > Fixes: aeda9adebab8 ("PCI/ASPM: Configure L1 substate settings") > Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> Applied to pci/aspm for v5.7, thanks! I also added a stable tag for v4.11+. > --- > change since v1: > 1. Add fixes tag in the commit message > 2. change category to ASPM from PM in the subject > Link: https://lore.kernel.org/linux-pci/20200312194202.GA162085@google.com/ > > drivers/pci/pcie/aspm.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c > index 0dcd443..c2596e7 100644 > --- a/drivers/pci/pcie/aspm.c > +++ b/drivers/pci/pcie/aspm.c > @@ -747,9 +747,9 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) > > /* Enable what we need to enable */ > pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, > - PCI_L1SS_CAP_L1_PM_SS, val); > + PCI_L1SS_CTL1_L1SS_MASK, val); > pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, > - PCI_L1SS_CAP_L1_PM_SS, val); > + PCI_L1SS_CTL1_L1SS_MASK, val); > } > > static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val) > -- > 2.8.1 >
diff --git a/drivers/pci/pcie/aspm.c b/drivers/pci/pcie/aspm.c index 0dcd443..c2596e7 100644 --- a/drivers/pci/pcie/aspm.c +++ b/drivers/pci/pcie/aspm.c @@ -747,9 +747,9 @@ static void pcie_config_aspm_l1ss(struct pcie_link_state *link, u32 state) /* Enable what we need to enable */ pci_clear_and_set_dword(parent, up_cap_ptr + PCI_L1SS_CTL1, - PCI_L1SS_CAP_L1_PM_SS, val); + PCI_L1SS_CTL1_L1SS_MASK, val); pci_clear_and_set_dword(child, dw_cap_ptr + PCI_L1SS_CTL1, - PCI_L1SS_CAP_L1_PM_SS, val); + PCI_L1SS_CTL1_L1SS_MASK, val); } static void pcie_config_aspm_dev(struct pci_dev *pdev, u32 val)
We enable proper L1 substates in the end of pcie_config_aspm_l1ss(). It's PCI_L1SS_CTL1_L1SS_MASK field should we set in PCI_L1SS_CTL1 register rather than PCI_L1SS_CAP_L1_PM_SS. Fixes: aeda9adebab8 ("PCI/ASPM: Configure L1 substate settings") Signed-off-by: Yicong Yang <yangyicong@hisilicon.com> --- change since v1: 1. Add fixes tag in the commit message 2. change category to ASPM from PM in the subject Link: https://lore.kernel.org/linux-pci/20200312194202.GA162085@google.com/ drivers/pci/pcie/aspm.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) -- 2.8.1