| Message ID | c633e31b9ceb238153d8f767a2d5681deaaa8985.1570376078.git.simon@simonsouth.net |
|---|---|
| State | Accepted |
| Commit | 18c24c11778c0571b6b559c02d1d58d65a8e44c1 |
| Delegated to: | Kever Yang |
| Headers | show |
| Series | Fix memory instability on ROCK64 | expand |
On 2019/10/7 上午12:28, Simon South wrote: > Fix a pair of tests in phy_dll_bypass_set() that used incorrect units > for the DDR frequency, causing the DRAM controller to be misconfigured > in most cases. > > Signed-off-by: Simon South <simon@simonsouth.net> Reviewed-by: Kever Yang<kever.yang@rock-chips.com> Thanks, - Kever > --- > drivers/ram/rockchip/sdram_rk3328.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c > index 656696ac3c..0541bbadf0 100644 > --- a/drivers/ram/rockchip/sdram_rk3328.c > +++ b/drivers/ram/rockchip/sdram_rk3328.c > @@ -311,12 +311,12 @@ static void phy_dll_bypass_set(struct dram_info *dram, u32 freq) > setbits_le32(PHY_REG(phy_base, 0x56), 1 << 4); > clrbits_le32(PHY_REG(phy_base, 0x57), 1 << 3); > > - if (freq <= (400 * MHz)) > + if (freq <= 400) > /* DLL bypass */ > setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); > else > clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); > - if (freq <= (680 * MHz)) > + if (freq <= 680) > tmp = 2; > else > tmp = 1;
On 2019/10/8 上午10:55, Kever Yang wrote: > > On 2019/10/7 上午12:28, Simon South wrote: >> Fix a pair of tests in phy_dll_bypass_set() that used incorrect units >> for the DDR frequency, causing the DRAM controller to be misconfigured >> in most cases. >> >> Signed-off-by: Simon South <simon@simonsouth.net> > > > Reviewed-by: Kever Yang<kever.yang@rock-chips.com> Applied to u-boot-rockchip master. > > > Thanks, > - Kever >> --- >> drivers/ram/rockchip/sdram_rk3328.c | 4 ++-- >> 1 file changed, 2 insertions(+), 2 deletions(-) >> >> diff --git a/drivers/ram/rockchip/sdram_rk3328.c >> b/drivers/ram/rockchip/sdram_rk3328.c >> index 656696ac3c..0541bbadf0 100644 >> --- a/drivers/ram/rockchip/sdram_rk3328.c >> +++ b/drivers/ram/rockchip/sdram_rk3328.c >> @@ -311,12 +311,12 @@ static void phy_dll_bypass_set(struct dram_info >> *dram, u32 freq) >> setbits_le32(PHY_REG(phy_base, 0x56), 1 << 4); >> clrbits_le32(PHY_REG(phy_base, 0x57), 1 << 3); >> - if (freq <= (400 * MHz)) >> + if (freq <= 400) >> /* DLL bypass */ >> setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); >> else >> clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); >> - if (freq <= (680 * MHz)) >> + if (freq <= 680) >> tmp = 2; >> else >> tmp = 1; > > > _______________________________________________ > U-Boot mailing list > U-Boot@lists.denx.de > https://lists.denx.de/listinfo/u-boot
diff --git a/drivers/ram/rockchip/sdram_rk3328.c b/drivers/ram/rockchip/sdram_rk3328.c index 656696ac3c..0541bbadf0 100644 --- a/drivers/ram/rockchip/sdram_rk3328.c +++ b/drivers/ram/rockchip/sdram_rk3328.c @@ -311,12 +311,12 @@ static void phy_dll_bypass_set(struct dram_info *dram, u32 freq) setbits_le32(PHY_REG(phy_base, 0x56), 1 << 4); clrbits_le32(PHY_REG(phy_base, 0x57), 1 << 3); - if (freq <= (400 * MHz)) + if (freq <= 400) /* DLL bypass */ setbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); else clrbits_le32(PHY_REG(phy_base, 0xa4), 0x1f); - if (freq <= (680 * MHz)) + if (freq <= 680) tmp = 2; else tmp = 1;
Fix a pair of tests in phy_dll_bypass_set() that used incorrect units for the DDR frequency, causing the DRAM controller to be misconfigured in most cases. Signed-off-by: Simon South <simon@simonsouth.net> --- drivers/ram/rockchip/sdram_rk3328.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)