diff mbox series

[v2] riscv: sifive_test: Add reset functionality

Message ID 1567698916-28260-1-git-send-email-bmeng.cn@gmail.com
State New
Headers show
Series [v2] riscv: sifive_test: Add reset functionality | expand

Commit Message

Bin Meng Sept. 5, 2019, 3:55 p.m. UTC 
This adds a reset opcode for sifive_test device to trigger a system
reset for testing purpose.

Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
Reviewed-by: Palmer Dabbelt <palmer@sifive.com>

---

Changes in v2:
- fix build error in the "for-master" branch of Palmer's RISC-V repo
  that was rebased on QEMU master

 hw/riscv/sifive_test.c         | 4 ++++
 include/hw/riscv/sifive_test.h | 3 ++-
 2 files changed, 6 insertions(+), 1 deletion(-)

Comments

Bin Meng Sept. 5, 2019, 3:57 p.m. UTC | #1 
Hi Palmer,

On Thu, Sep 5, 2019 at 11:55 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>
> This adds a reset opcode for sifive_test device to trigger a system
> reset for testing purpose.
>
> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>
> ---
>
> Changes in v2:
> - fix build error in the "for-master" branch of Palmer's RISC-V repo
>   that was rebased on QEMU master
>
>  hw/riscv/sifive_test.c         | 4 ++++
>  include/hw/riscv/sifive_test.h | 3 ++-
>  2 files changed, 6 insertions(+), 1 deletion(-)
>

Please drop the already applied v1 patch in your "for-master" branch
and apply this v2.

After you rebased the "for-master' branch, this patch no longer build
any more due to changes in QEMU master.

Regards,
Bin
Palmer Dabbelt Sept. 5, 2019, 7:16 p.m. UTC | #2 
On Thu, 05 Sep 2019 08:57:44 PDT (-0700), bmeng.cn@gmail.com wrote:
> Hi Palmer,
>
> On Thu, Sep 5, 2019 at 11:55 PM Bin Meng <bmeng.cn@gmail.com> wrote:
>>
>> This adds a reset opcode for sifive_test device to trigger a system
>> reset for testing purpose.
>>
>> Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
>> Reviewed-by: Palmer Dabbelt <palmer@sifive.com>
>>
>> ---
>>
>> Changes in v2:
>> - fix build error in the "for-master" branch of Palmer's RISC-V repo
>>   that was rebased on QEMU master
>>
>>  hw/riscv/sifive_test.c         | 4 ++++
>>  include/hw/riscv/sifive_test.h | 3 ++-
>>  2 files changed, 6 insertions(+), 1 deletion(-)
>>
>
> Please drop the already applied v1 patch in your "for-master" branch
> and apply this v2.
>
> After you rebased the "for-master' branch, this patch no longer build
> any more due to changes in QEMU master.
>
> Regards,
> Bin

Thanks!
diff mbox series

Patch

diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c
index afbb3aa..3557e16 100644
--- a/hw/riscv/sifive_test.c
+++ b/hw/riscv/sifive_test.c
@@ -22,6 +22,7 @@ 
 #include "hw/hw.h"
 #include "hw/sysbus.h"
 #include "qemu/module.h"
+#include "sysemu/runstate.h"
 #include "target/riscv/cpu.h"
 #include "hw/hw.h"
 #include "hw/riscv/sifive_test.h"
@@ -42,6 +43,9 @@  static void sifive_test_write(void *opaque, hwaddr addr,
             exit(code);
         case FINISHER_PASS:
             exit(0);
+        case FINISHER_RESET:
+            qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+            return;
         default:
             break;
         }
diff --git a/include/hw/riscv/sifive_test.h b/include/hw/riscv/sifive_test.h
index 3a603a6..1ec416a 100644
--- a/include/hw/riscv/sifive_test.h
+++ b/include/hw/riscv/sifive_test.h
@@ -36,7 +36,8 @@  typedef struct SiFiveTestState {
 
 enum {
     FINISHER_FAIL = 0x3333,
-    FINISHER_PASS = 0x5555
+    FINISHER_PASS = 0x5555,
+    FINISHER_RESET = 0x7777
 };
 
 DeviceState *sifive_test_create(hwaddr addr);