| Message ID | 1299124136-26859-1-git-send-email-Priyanka.Jain@freescale.com |
|---|---|
| State | Accepted, archived |
| Headers | show |
On Mar 2, 2011, at 9:48 PM, Priyanka Jain wrote: > - Timeout counter value is set as DTOCV bits in SYSCTL register > For counter value set as timeout, > Timeout period = (2^(timeout + 13)) SD Clock cycles > > - As per 4.6.2.2 section of SD Card specification v2.00, host should > cofigure timeout period value to minimum 0.25 sec. > > - Number of SD Clock cycles for 0.25sec should be minimum > (SD Clock/sec * 0.25 sec) SD Clock cycles > = (mmc->tran_speed * 1/4) SD Clock cycles > > - Calculating timeout based on > (2^(timeout + 13)) >= mmc->tran_speed * 1/4 > Taking log2 both the sides and rounding up to next power of 2 > => timeout + 13 = log2(mmc->tran_speed/4) + 1 > > Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> > Signed-off-by: Andy Fleming <afleming@freescale.com> > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > Acked-by: Mingkai Hu <Mingkai.Hu@freescale.com> > --- > Changes for v3: > Including code changes of v1 as suggested by Stefano Babic > > Changes for v2: > Added proper description as suggested by Wolfgang Denk > > drivers/mmc/fsl_esdhc.c | 16 +++++++++++++++- > 1 files changed, 15 insertions(+), 1 deletions(-) Stefano, Got a chance to test on imx? Would like this fix in v2011.03 - k
On 03/03/2011 04:48 AM, Priyanka Jain wrote: > - Timeout counter value is set as DTOCV bits in SYSCTL register > For counter value set as timeout, > Timeout period = (2^(timeout + 13)) SD Clock cycles > > - As per 4.6.2.2 section of SD Card specification v2.00, host should > cofigure timeout period value to minimum 0.25 sec. > > - Number of SD Clock cycles for 0.25sec should be minimum > (SD Clock/sec * 0.25 sec) SD Clock cycles > = (mmc->tran_speed * 1/4) SD Clock cycles > > - Calculating timeout based on > (2^(timeout + 13)) >= mmc->tran_speed * 1/4 > Taking log2 both the sides and rounding up to next power of 2 > => timeout + 13 = log2(mmc->tran_speed/4) + 1 > > Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> > Signed-off-by: Andy Fleming <afleming@freescale.com> > Signed-off-by: Kumar Gala <galak@kernel.crashing.org> > Acked-by: Mingkai Hu <Mingkai.Hu@freescale.com> > --- Tested on a i.MX51 board. Tested-by: Stefano Babic <sbabic@denx.de> Best regards, Stefano Babic
On Mar 7, 2011, at 3:41 AM, Stefano Babic wrote: > On 03/03/2011 04:48 AM, Priyanka Jain wrote: >> - Timeout counter value is set as DTOCV bits in SYSCTL register >> For counter value set as timeout, >> Timeout period = (2^(timeout + 13)) SD Clock cycles >> >> - As per 4.6.2.2 section of SD Card specification v2.00, host should >> cofigure timeout period value to minimum 0.25 sec. >> >> - Number of SD Clock cycles for 0.25sec should be minimum >> (SD Clock/sec * 0.25 sec) SD Clock cycles >> = (mmc->tran_speed * 1/4) SD Clock cycles >> >> - Calculating timeout based on >> (2^(timeout + 13)) >= mmc->tran_speed * 1/4 >> Taking log2 both the sides and rounding up to next power of 2 >> => timeout + 13 = log2(mmc->tran_speed/4) + 1 >> >> Signed-off-by: Priyanka Jain <Priyanka.Jain@freescale.com> >> Signed-off-by: Andy Fleming <afleming@freescale.com> >> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> >> Acked-by: Mingkai Hu <Mingkai.Hu@freescale.com> >> --- > > Tested on a i.MX51 board. > > Tested-by: Stefano Babic <sbabic@denx.de> > > Best regards, > Stefano Babic thanks applied. - k
diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index a368fe6..359d939 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -207,7 +207,21 @@ static int esdhc_setup_data(struct mmc *mmc, struct mmc_data *data) esdhc_write32(®s->blkattr, data->blocks << 16 | data->blocksize); /* Calculate the timeout period for data transactions */ - timeout = fls(mmc->tran_speed/10) - 1; + /* + * 1)Timeout period = (2^(timeout+13)) SD Clock cycles + * 2)Timeout period should be minimum 0.250sec as per SD Card spec + * So, Number of SD Clock cycles for 0.25sec should be minimum + * (SD Clock/sec * 0.25 sec) SD Clock cycles + * = (mmc->tran_speed * 1/4) SD Clock cycles + * As 1) >= 2) + * => (2^(timeout+13)) >= mmc->tran_speed * 1/4 + * Taking log2 both the sides + * => timeout + 13 >= log2(mmc->tran_speed/4) + * Rounding up to next power of 2 + * => timeout + 13 = log2(mmc->tran_speed/4) + 1 + * => timeout + 13 = fls(mmc->tran_speed/4) + */ + timeout = fls(mmc->tran_speed/4); timeout -= 13; if (timeout > 14)