diff mbox series

[U-Boot,v2,10/18] net: gmac_rockchip: Add rk3328 gmac support

Message ID 1510219240-79081-1-git-send-email-david.wu@rock-chips.com
State Changes Requested
Delegated to: Philipp Tomsich
Headers show
Series None | expand

Commit Message

David Wu Nov. 9, 2017, 9:20 a.m. UTC
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Content preview:  The GMAC2IO in the RK3328 once again is identical to the incarnation
   in the RK3288 and the RK3399, except for where some of the configuration
  and control registers are located in the GRF. This adds the RK3328-specific
   logic necessary to reuse this driver. [...] 

Content analysis details:   (5.7 points, 5.0 required)

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The GMAC2IO in the RK3328 once again is identical to the incarnation in
the RK3288 and the RK3399, except for where some of the configuration
and control registers are located in the GRF.

This adds the RK3328-specific logic necessary to reuse this driver.

Signed-off-by: David Wu <david.wu@rock-chips.com>
---

Changes in v2:
- New patch

 drivers/net/gmac_rockchip.c | 85 +++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 85 insertions(+)

Comments

Philipp Tomsich Nov. 20, 2017, 3:05 p.m. UTC | #1
> Spam detection software, running on the system "lists.denx.de",
> has identified this incoming email as possible spam.  The original
> message has been attached to this so you can view it or label
> similar future email.  If you have any questions, see
> @@CONTACT_ADDRESS@@ for details.
> 
> Content preview:  The GMAC2IO in the RK3328 once again is identical to the incarnation
>    in the RK3288 and the RK3399, except for where some of the configuration
>   and control registers are located in the GRF. This adds the RK3328-specific
>    logic necessary to reuse this driver. [...] 
> 
> Content analysis details:   (5.7 points, 5.0 required)
> 
>  pts rule name              description
> ---- ---------------------- --------------------------------------------------
>  2.7 RCVD_IN_PSBL           RBL: Received via a relay in PSBL
>                             [211.157.147.134 listed in psbl.surriel.com]
>  0.6 RCVD_IN_SORBS_WEB      RBL: SORBS: sender is an abusable web server
>                             [58.22.7.114 listed in dnsbl.sorbs.net]
>  2.4 RCVD_IN_MSPIKE_L5      RBL: Very bad reputation (-5)
>                             [211.157.147.134 listed in bl.mailspike.net]
>  0.0 RCVD_IN_MSPIKE_BL      Mailspike blacklisted
> The GMAC2IO in the RK3328 once again is identical to the incarnation in
> the RK3288 and the RK3399, except for where some of the configuration
> and control registers are located in the GRF.
> 
> This adds the RK3328-specific logic necessary to reuse this driver.
> 
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> ---
> 
> Changes in v2:
> - New patch
> 
>  drivers/net/gmac_rockchip.c | 85 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 85 insertions(+)
> 

Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Philipp Tomsich Nov. 25, 2017, 11:51 p.m. UTC | #2
> Spam detection software, running on the system "lists.denx.de",
> has identified this incoming email as possible spam.  The original
> message has been attached to this so you can view it or label
> similar future email.  If you have any questions, see
> @@CONTACT_ADDRESS@@ for details.
> 
> Content preview:  The GMAC2IO in the RK3328 once again is identical to the incarnation
>    in the RK3288 and the RK3399, except for where some of the configuration
>   and control registers are located in the GRF. This adds the RK3328-specific
>    logic necessary to reuse this driver. [...] 
> 
> Content analysis details:   (5.7 points, 5.0 required)
> 
>  pts rule name              description
> ---- ---------------------- --------------------------------------------------
>  2.7 RCVD_IN_PSBL           RBL: Received via a relay in PSBL
>                             [211.157.147.134 listed in psbl.surriel.com]
>  0.6 RCVD_IN_SORBS_WEB      RBL: SORBS: sender is an abusable web server
>                             [58.22.7.114 listed in dnsbl.sorbs.net]
>  2.4 RCVD_IN_MSPIKE_L5      RBL: Very bad reputation (-5)
>                             [211.157.147.134 listed in bl.mailspike.net]
>  0.0 RCVD_IN_MSPIKE_BL      Mailspike blacklisted
> The GMAC2IO in the RK3328 once again is identical to the incarnation in
> the RK3288 and the RK3399, except for where some of the configuration
> and control registers are located in the GRF.
> 
> This adds the RK3328-specific logic necessary to reuse this driver.
> 
> Signed-off-by: David Wu <david.wu@rock-chips.com>
> Acked-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> ---
> 
> Changes in v2:
> - New patch
> 
>  drivers/net/gmac_rockchip.c | 85 +++++++++++++++++++++++++++++++++++++++++++++
>  1 file changed, 85 insertions(+)
> 

Reviewed-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
diff mbox series

Patch

diff --git a/drivers/net/gmac_rockchip.c b/drivers/net/gmac_rockchip.c
index 22e3941..f24c347 100644
--- a/drivers/net/gmac_rockchip.c
+++ b/drivers/net/gmac_rockchip.c
@@ -16,6 +16,7 @@ 
 #include <asm/arch/clock.h>
 #include <asm/arch/hardware.h>
 #include <asm/arch/grf_rk3288.h>
+#include <asm/arch/grf_rk3328.h>
 #include <asm/arch/grf_rk3368.h>
 #include <asm/arch/grf_rk3399.h>
 #include <asm/arch/grf_rv1108.h>
@@ -86,6 +87,39 @@  static int rk3288_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 	return 0;
 }
 
+static int rk3328_gmac_fix_mac_speed(struct dw_eth_dev *priv)
+{
+	struct rk3328_grf_regs *grf;
+	int clk;
+	enum {
+		RK3328_GMAC_CLK_SEL_SHIFT = 11,
+		RK3328_GMAC_CLK_SEL_MASK  = GENMASK(12, 11),
+		RK3328_GMAC_CLK_SEL_125M  = 0 << 11,
+		RK3328_GMAC_CLK_SEL_25M   = 3 << 11,
+		RK3328_GMAC_CLK_SEL_2_5M  = 2 << 11,
+	};
+
+	switch (priv->phydev->speed) {
+	case 10:
+		clk = RK3328_GMAC_CLK_SEL_2_5M;
+		break;
+	case 100:
+		clk = RK3328_GMAC_CLK_SEL_25M;
+		break;
+	case 1000:
+		clk = RK3328_GMAC_CLK_SEL_125M;
+		break;
+	default:
+		debug("Unknown phy speed: %d\n", priv->phydev->speed);
+		return -EINVAL;
+	}
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->mac_con[1], RK3328_GMAC_CLK_SEL_MASK, clk);
+
+	return 0;
+}
+
 static int rk3368_gmac_fix_mac_speed(struct dw_eth_dev *priv)
 {
 	struct rk3368_grf *grf;
@@ -199,6 +233,50 @@  static void rk3288_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 		     pdata->tx_delay << RK3288_CLK_TX_DL_CFG_GMAC_SHIFT);
 }
 
+static void rk3328_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
+{
+	struct rk3328_grf_regs *grf;
+	enum {
+		RK3328_RMII_MODE_SHIFT = 9,
+		RK3328_RMII_MODE_MASK  = BIT(9),
+
+		RK3328_GMAC_PHY_INTF_SEL_SHIFT = 4,
+		RK3328_GMAC_PHY_INTF_SEL_MASK  = GENMASK(6, 4),
+		RK3328_GMAC_PHY_INTF_SEL_RGMII = BIT(4),
+
+		RK3328_RXCLK_DLY_ENA_GMAC_MASK = BIT(1),
+		RK3328_RXCLK_DLY_ENA_GMAC_DISABLE = 0,
+		RK3328_RXCLK_DLY_ENA_GMAC_ENABLE = BIT(1),
+
+		RK3328_TXCLK_DLY_ENA_GMAC_MASK = BIT(0),
+		RK3328_TXCLK_DLY_ENA_GMAC_DISABLE = 0,
+		RK3328_TXCLK_DLY_ENA_GMAC_ENABLE = BIT(0),
+	};
+	enum {
+		RK3328_CLK_RX_DL_CFG_GMAC_SHIFT = 0x7,
+		RK3328_CLK_RX_DL_CFG_GMAC_MASK = GENMASK(13, 7),
+
+		RK3328_CLK_TX_DL_CFG_GMAC_SHIFT = 0x0,
+		RK3328_CLK_TX_DL_CFG_GMAC_MASK = GENMASK(6, 0),
+	};
+
+	grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
+	rk_clrsetreg(&grf->mac_con[1],
+		     RK3328_RMII_MODE_MASK |
+		     RK3328_GMAC_PHY_INTF_SEL_MASK |
+		     RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+		     RK3328_TXCLK_DLY_ENA_GMAC_MASK,
+		     RK3328_GMAC_PHY_INTF_SEL_RGMII |
+		     RK3328_RXCLK_DLY_ENA_GMAC_MASK |
+		     RK3328_TXCLK_DLY_ENA_GMAC_ENABLE);
+
+	rk_clrsetreg(&grf->mac_con[0],
+		     RK3328_CLK_RX_DL_CFG_GMAC_MASK |
+		     RK3328_CLK_TX_DL_CFG_GMAC_MASK,
+		     pdata->rx_delay << RK3328_CLK_RX_DL_CFG_GMAC_SHIFT |
+		     pdata->tx_delay << RK3328_CLK_TX_DL_CFG_GMAC_SHIFT);
+}
+
 static void rk3368_gmac_set_to_rgmii(struct gmac_rockchip_platdata *pdata)
 {
 	struct rk3368_grf *grf;
@@ -347,6 +425,11 @@  const struct rk_gmac_ops rk3288_gmac_ops = {
 	.set_to_rgmii = rk3288_gmac_set_to_rgmii,
 };
 
+const struct rk_gmac_ops rk3328_gmac_ops = {
+	.fix_mac_speed = rk3328_gmac_fix_mac_speed,
+	.set_to_rgmii = rk3328_gmac_set_to_rgmii,
+};
+
 const struct rk_gmac_ops rk3368_gmac_ops = {
 	.fix_mac_speed = rk3368_gmac_fix_mac_speed,
 	.set_to_rgmii = rk3368_gmac_set_to_rgmii,
@@ -365,6 +448,8 @@  const struct rk_gmac_ops rv1108_gmac_ops = {
 static const struct udevice_id rockchip_gmac_ids[] = {
 	{ .compatible = "rockchip,rk3288-gmac",
 	  .data = (ulong)&rk3288_gmac_ops },
+	{ .compatible = "rockchip,rk3328-gmac",
+	  .data = (ulong)&rk3328_gmac_ops },
 	{ .compatible = "rockchip,rk3368-gmac",
 	  .data = (ulong)&rk3368_gmac_ops },
 	{ .compatible = "rockchip,rk3399-gmac",