| Message ID | 1441217278-21618-1-git-send-email-afleming@gmail.com (mailing list archive) |
|---|---|
| State | Accepted |
| Delegated to: | Scott Wood |
| Headers | show |
ping? I'd love if this could go in for 4.3 On Wed, Sep 2, 2015 at 1:07 PM, Andy Fleming <afleming@gmail.com> wrote: > This board uses a P5020 chip, and boots just fine using > the corenet_generic code. The device tree is very similar to the > P5020DS, except that there is no Flash memory. The environment is, > instead, stored on an MMC card on the motherboard. > > Signed-off-by: Andy Fleming <afleming@gmail.com> > --- > v2: Moved dts to cyrus_p5020.dts so we can add a p5040 version later > Corrected the model/compatible to varisys,CYRUS > > arch/powerpc/boot/dts/cyrus_p5020.dts | 155 ++++++++++++++++++++++++++ > arch/powerpc/platforms/85xx/corenet_generic.c | 1 + > 2 files changed, 156 insertions(+) > create mode 100644 arch/powerpc/boot/dts/cyrus_p5020.dts > > diff --git a/arch/powerpc/boot/dts/cyrus_p5020.dts b/arch/powerpc/boot/dts/cyrus_p5020.dts > new file mode 100644 > index 0000000..493c6d6 > --- /dev/null > +++ b/arch/powerpc/boot/dts/cyrus_p5020.dts > @@ -0,0 +1,155 @@ > +/* > + * Cyrus 5020 Device Tree Source, based on p5020ds.dts > + * > + * Copyright 2015 Andy Fleming > + * > + * p5020ds.dts copyright: > + * Copyright 2010 - 2014 Freescale Semiconductor Inc. > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms of the GNU General Public License as published by the > + * Free Software Foundation; either version 2 of the License, or (at your > + * option) any later version. > + */ > + > +/include/ "fsl/p5020si-pre.dtsi" > + > +/ { > + model = "varisys,CYRUS"; > + compatible = "varisys,CYRUS"; > + #address-cells = <2>; > + #size-cells = <2>; > + interrupt-parent = <&mpic>; > + > + memory { > + device_type = "memory"; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + bman_fbpr: bman-fbpr { > + size = <0 0x1000000>; > + alignment = <0 0x1000000>; > + }; > + qman_fqd: qman-fqd { > + size = <0 0x400000>; > + alignment = <0 0x400000>; > + }; > + qman_pfdr: qman-pfdr { > + size = <0 0x2000000>; > + alignment = <0 0x2000000>; > + }; > + }; > + > + dcsr: dcsr@f00000000 { > + ranges = <0x00000000 0xf 0x00000000 0x01008000>; > + }; > + > + bportals: bman-portals@ff4000000 { > + ranges = <0x0 0xf 0xf4000000 0x200000>; > + }; > + > + qportals: qman-portals@ff4200000 { > + ranges = <0x0 0xf 0xf4200000 0x200000>; > + }; > + > + soc: soc@ffe000000 { > + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; > + reg = <0xf 0xfe000000 0 0x00001000>; > + spi@110000 { > + }; > + > + i2c@118100 { > + }; > + > + i2c@119100 { > + rtc@6f { > + compatible = "microchip,mcp7941x"; > + reg = <0x6f>; > + }; > + }; > + }; > + > + rio: rapidio@ffe0c0000 { > + reg = <0xf 0xfe0c0000 0 0x11000>; > + > + port1 { > + ranges = <0 0 0xc 0x20000000 0 0x10000000>; > + }; > + port2 { > + ranges = <0 0 0xc 0x30000000 0 0x10000000>; > + }; > + }; > + > + lbc: localbus@ffe124000 { > + reg = <0xf 0xfe124000 0 0x1000>; > + ranges = <0 0 0xf 0xe8000000 0x08000000 > + 2 0 0xf 0xffa00000 0x00040000 > + 3 0 0xf 0xffdf0000 0x00008000>; > + }; > + > + pci0: pcie@ffe200000 { > + reg = <0xf 0xfe200000 0 0x1000>; > + ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 > + 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; > + pcie@0 { > + ranges = <0x02000000 0 0xe0000000 > + 0x02000000 0 0xe0000000 > + 0 0x20000000 > + > + 0x01000000 0 0x00000000 > + 0x01000000 0 0x00000000 > + 0 0x00010000>; > + }; > + }; > + > + pci1: pcie@ffe201000 { > + reg = <0xf 0xfe201000 0 0x1000>; > + ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 > + 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; > + pcie@0 { > + ranges = <0x02000000 0 0xe0000000 > + 0x02000000 0 0xe0000000 > + 0 0x20000000 > + > + 0x01000000 0 0x00000000 > + 0x01000000 0 0x00000000 > + 0 0x00010000>; > + }; > + }; > + > + pci2: pcie@ffe202000 { > + reg = <0xf 0xfe202000 0 0x1000>; > + ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 > + 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; > + pcie@0 { > + ranges = <0x02000000 0 0xe0000000 > + 0x02000000 0 0xe0000000 > + 0 0x20000000 > + > + 0x01000000 0 0x00000000 > + 0x01000000 0 0x00000000 > + 0 0x00010000>; > + }; > + }; > + > + pci3: pcie@ffe203000 { > + reg = <0xf 0xfe203000 0 0x1000>; > + ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 > + 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; > + pcie@0 { > + ranges = <0x02000000 0 0xe0000000 > + 0x02000000 0 0xe0000000 > + 0 0x20000000 > + > + 0x01000000 0 0x00000000 > + 0x01000000 0 0x00000000 > + 0 0x00010000>; > + }; > + }; > +}; > + > +/include/ "fsl/p5020si-post.dtsi" > diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c > index b395571..76e521e 100644 > --- a/arch/powerpc/platforms/85xx/corenet_generic.c > +++ b/arch/powerpc/platforms/85xx/corenet_generic.c > @@ -161,6 +161,7 @@ static const char * const boards[] __initconst = { > "fsl,T1042RDB", > "fsl,T1042RDB_PI", > "keymile,kmcoge4", > + "varisys,CYRUS", > NULL > }; > > -- > 1.9.1 >
On Thu, 2015-09-10 at 20:51 -0500, Andy Fleming wrote: > ping? I'd love if this could go in for 4.3 It's way too late for 4.3. -Scott > > On Wed, Sep 2, 2015 at 1:07 PM, Andy Fleming <afleming@gmail.com> wrote: > > This board uses a P5020 chip, and boots just fine using > > the corenet_generic code. The device tree is very similar to the > > P5020DS, except that there is no Flash memory. The environment is, > > instead, stored on an MMC card on the motherboard. > > > > Signed-off-by: Andy Fleming <afleming@gmail.com> > > --- > > v2: Moved dts to cyrus_p5020.dts so we can add a p5040 version later > > Corrected the model/compatible to varisys,CYRUS > > > > arch/powerpc/boot/dts/cyrus_p5020.dts | 155 > > ++++++++++++++++++++++++++ > > arch/powerpc/platforms/85xx/corenet_generic.c | 1 + > > 2 files changed, 156 insertions(+) > > create mode 100644 arch/powerpc/boot/dts/cyrus_p5020.dts > > > > diff --git a/arch/powerpc/boot/dts/cyrus_p5020.dts > > b/arch/powerpc/boot/dts/cyrus_p5020.dts > > new file mode 100644 > > index 0000000..493c6d6 > > --- /dev/null > > +++ b/arch/powerpc/boot/dts/cyrus_p5020.dts > > @@ -0,0 +1,155 @@ > > +/* > > + * Cyrus 5020 Device Tree Source, based on p5020ds.dts > > + * > > + * Copyright 2015 Andy Fleming > > + * > > + * p5020ds.dts copyright: > > + * Copyright 2010 - 2014 Freescale Semiconductor Inc. > > + * > > + * This program is free software; you can redistribute it and/or modify > > it > > + * under the terms of the GNU General Public License as published by > > the > > + * Free Software Foundation; either version 2 of the License, or (at > > your > > + * option) any later version. > > + */ > > + > > +/include/ "fsl/p5020si-pre.dtsi" > > + > > +/ { > > + model = "varisys,CYRUS"; > > + compatible = "varisys,CYRUS"; > > + #address-cells = <2>; > > + #size-cells = <2>; > > + interrupt-parent = <&mpic>; > > + > > + memory { > > + device_type = "memory"; > > + }; > > + > > + reserved-memory { > > + #address-cells = <2>; > > + #size-cells = <2>; > > + ranges; > > + > > + bman_fbpr: bman-fbpr { > > + size = <0 0x1000000>; > > + alignment = <0 0x1000000>; > > + }; > > + qman_fqd: qman-fqd { > > + size = <0 0x400000>; > > + alignment = <0 0x400000>; > > + }; > > + qman_pfdr: qman-pfdr { > > + size = <0 0x2000000>; > > + alignment = <0 0x2000000>; > > + }; > > + }; > > + > > + dcsr: dcsr@f00000000{ > > + ranges = <0x00000000 0xf 0x00000000 0x01008000>; > > + }; > > + > > + bportals: bman-portals@ff4000000{ > > + ranges = <0x0 0xf 0xf4000000 0x200000>; > > + }; > > + > > + qportals: qman-portals@ff4200000{ > > + ranges = <0x0 0xf 0xf4200000 0x200000>; > > + }; > > + > > + soc: soc@ffe000000{ > > + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; > > + reg = <0xf 0xfe000000 0 0x00001000>; > > + spi@110000{ > > + }; > > + > > + i2c@118100{ > > + }; > > + > > + i2c@119100{ > > + rtc@6f{ > > + compatible = "microchip,mcp7941x"; > > + reg = <0x6f>; > > + }; > > + }; > > + }; > > + > > + rio: rapidio@ffe0c0000{ > > + reg = <0xf 0xfe0c0000 0 0x11000>; > > + > > + port1 { > > + ranges = <0 0 0xc 0x20000000 0 0x10000000>; > > + }; > > + port2 { > > + ranges = <0 0 0xc 0x30000000 0 0x10000000>; > > + }; > > + }; > > + > > + lbc: localbus@ffe124000{ > > + reg = <0xf 0xfe124000 0 0x1000>; > > + ranges = <0 0 0xf 0xe8000000 0x08000000 > > + 2 0 0xf 0xffa00000 0x00040000 > > + 3 0 0xf 0xffdf0000 0x00008000>; > > + }; > > + > > + pci0: pcie@ffe200000{ > > + reg = <0xf 0xfe200000 0 0x1000>; > > + ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 > > 0x20000000 > > + 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 > > 0x00010000>; > > + pcie@0{ > > + ranges = <0x02000000 0 0xe0000000 > > + 0x02000000 0 0xe0000000 > > + 0 0x20000000 > > + > > + 0x01000000 0 0x00000000 > > + 0x01000000 0 0x00000000 > > + 0 0x00010000>; > > + }; > > + }; > > + > > + pci1: pcie@ffe201000{ > > + reg = <0xf 0xfe201000 0 0x1000>; > > + ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 > > 0x20000000 > > + 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 > > 0x00010000>; > > + pcie@0{ > > + ranges = <0x02000000 0 0xe0000000 > > + 0x02000000 0 0xe0000000 > > + 0 0x20000000 > > + > > + 0x01000000 0 0x00000000 > > + 0x01000000 0 0x00000000 > > + 0 0x00010000>; > > + }; > > + }; > > + > > + pci2: pcie@ffe202000{ > > + reg = <0xf 0xfe202000 0 0x1000>; > > + ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 > > 0x20000000 > > + 0x01000000 0 0x00000000 0xf 0xf8020000 0 > > 0x00010000>; > > + pcie@0{ > > + ranges = <0x02000000 0 0xe0000000 > > + 0x02000000 0 0xe0000000 > > + 0 0x20000000 > > + > > + 0x01000000 0 0x00000000 > > + 0x01000000 0 0x00000000 > > + 0 0x00010000>; > > + }; > > + }; > > + > > + pci3: pcie@ffe203000{ > > + reg = <0xf 0xfe203000 0 0x1000>; > > + ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 > > 0x20000000 > > + 0x01000000 0 0x00000000 0xf 0xf8030000 0 > > 0x00010000>; > > + pcie@0{ > > + ranges = <0x02000000 0 0xe0000000 > > + 0x02000000 0 0xe0000000 > > + 0 0x20000000 > > + > > + 0x01000000 0 0x00000000 > > + 0x01000000 0 0x00000000 > > + 0 0x00010000>; > > + }; > > + }; > > +}; > > + > > +/include/ "fsl/p5020si-post.dtsi" > > diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c > > b/arch/powerpc/platforms/85xx/corenet_generic.c > > index b395571..76e521e 100644 > > --- a/arch/powerpc/platforms/85xx/corenet_generic.c > > +++ b/arch/powerpc/platforms/85xx/corenet_generic.c > > @@ -161,6 +161,7 @@ static const char * const boards[] __initconst = { > > "fsl,T1042RDB", > > "fsl,T1042RDB_PI", > > "keymile,kmcoge4", > > + "varisys,CYRUS", > > NULL > > }; > > > > -- > > 1.9.1 > >
On Thu, Sep 10, 2015 at 8:53 PM, Scott Wood <scottwood@freescale.com> wrote: > On Thu, 2015-09-10 at 20:51 -0500, Andy Fleming wrote: >> ping? I'd love if this could go in for 4.3 > > It's way too late for 4.3. > > -Scott Argh. I was hoping that, as it's a one-line change to existing code it might be able to sneak in. Andy
On Thu, 2015-09-10 at 21:06 -0500, Andy Fleming wrote: > On Thu, Sep 10, 2015 at 8:53 PM, Scott Wood <scottwood@freescale.com> wrote: > > On Thu, 2015-09-10 at 20:51 -0500, Andy Fleming wrote: > > > ping? I'd love if this could go in for 4.3 > > > > It's way too late for 4.3. > > > > -Scott > > Argh. I was hoping that, as it's a one-line change to existing code it > might be able to sneak in. It's hard to call it "sneaking in" when a new pull request chain has to be created just for one patch. :-P Non-bugfixes need to be in my pull request to Michael before the merge window opens (and thus submitted long enough before that for me to have a chance to do a review/apply/build-test session), not a couple days before the merge window closes. Why does it matter if this is in 4.3 versus 4.4? -Scott
On Thu, Sep 10, 2015 at 9:13 PM, Scott Wood <scottwood@freescale.com> wrote: > On Thu, 2015-09-10 at 21:06 -0500, Andy Fleming wrote: >> On Thu, Sep 10, 2015 at 8:53 PM, Scott Wood <scottwood@freescale.com> wrote: >> > On Thu, 2015-09-10 at 20:51 -0500, Andy Fleming wrote: >> > > ping? I'd love if this could go in for 4.3 >> > >> > It's way too late for 4.3. >> > >> > -Scott >> >> Argh. I was hoping that, as it's a one-line change to existing code it >> might be able to sneak in. > > It's hard to call it "sneaking in" when a new pull request chain has to be > created just for one patch. :-P > > Non-bugfixes need to be in my pull request to Michael before the merge window > opens (and thus submitted long enough before that for me to have a chance to > do a review/apply/build-test session), not a couple days before the merge > window closes. Why does it matter if this is in 4.3 versus 4.4? > > -Scott > I definitely understand. To be fair, I submitted the patch 3 days after the window opened (not a couple before it closes), but that is still after the deadline. The only issue with it going into 4.4 is that the support isn't in mainline till 4.3 is tagged. It just creates a bigger lag between the hardware availability and upstream software availability. Bad timing on our part, I was just hoping. :) Andy
diff --git a/arch/powerpc/boot/dts/cyrus_p5020.dts b/arch/powerpc/boot/dts/cyrus_p5020.dts new file mode 100644 index 0000000..493c6d6 --- /dev/null +++ b/arch/powerpc/boot/dts/cyrus_p5020.dts @@ -0,0 +1,155 @@ +/* + * Cyrus 5020 Device Tree Source, based on p5020ds.dts + * + * Copyright 2015 Andy Fleming + * + * p5020ds.dts copyright: + * Copyright 2010 - 2014 Freescale Semiconductor Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the + * Free Software Foundation; either version 2 of the License, or (at your + * option) any later version. + */ + +/include/ "fsl/p5020si-pre.dtsi" + +/ { + model = "varisys,CYRUS"; + compatible = "varisys,CYRUS"; + #address-cells = <2>; + #size-cells = <2>; + interrupt-parent = <&mpic>; + + memory { + device_type = "memory"; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + bman_fbpr: bman-fbpr { + size = <0 0x1000000>; + alignment = <0 0x1000000>; + }; + qman_fqd: qman-fqd { + size = <0 0x400000>; + alignment = <0 0x400000>; + }; + qman_pfdr: qman-pfdr { + size = <0 0x2000000>; + alignment = <0 0x2000000>; + }; + }; + + dcsr: dcsr@f00000000 { + ranges = <0x00000000 0xf 0x00000000 0x01008000>; + }; + + bportals: bman-portals@ff4000000 { + ranges = <0x0 0xf 0xf4000000 0x200000>; + }; + + qportals: qman-portals@ff4200000 { + ranges = <0x0 0xf 0xf4200000 0x200000>; + }; + + soc: soc@ffe000000 { + ranges = <0x00000000 0xf 0xfe000000 0x1000000>; + reg = <0xf 0xfe000000 0 0x00001000>; + spi@110000 { + }; + + i2c@118100 { + }; + + i2c@119100 { + rtc@6f { + compatible = "microchip,mcp7941x"; + reg = <0x6f>; + }; + }; + }; + + rio: rapidio@ffe0c0000 { + reg = <0xf 0xfe0c0000 0 0x11000>; + + port1 { + ranges = <0 0 0xc 0x20000000 0 0x10000000>; + }; + port2 { + ranges = <0 0 0xc 0x30000000 0 0x10000000>; + }; + }; + + lbc: localbus@ffe124000 { + reg = <0xf 0xfe124000 0 0x1000>; + ranges = <0 0 0xf 0xe8000000 0x08000000 + 2 0 0xf 0xffa00000 0x00040000 + 3 0 0xf 0xffdf0000 0x00008000>; + }; + + pci0: pcie@ffe200000 { + reg = <0xf 0xfe200000 0 0x1000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x00000000 0x0 0x20000000 + 0x01000000 0 0x00000000 0xf 0xf8000000 0x0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x20000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci1: pcie@ffe201000 { + reg = <0xf 0xfe201000 0 0x1000>; + ranges = <0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000 + 0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x20000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci2: pcie@ffe202000 { + reg = <0xf 0xfe202000 0 0x1000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x40000000 0 0x20000000 + 0x01000000 0 0x00000000 0xf 0xf8020000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x20000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; + + pci3: pcie@ffe203000 { + reg = <0xf 0xfe203000 0 0x1000>; + ranges = <0x02000000 0 0xe0000000 0xc 0x60000000 0 0x20000000 + 0x01000000 0 0x00000000 0xf 0xf8030000 0 0x00010000>; + pcie@0 { + ranges = <0x02000000 0 0xe0000000 + 0x02000000 0 0xe0000000 + 0 0x20000000 + + 0x01000000 0 0x00000000 + 0x01000000 0 0x00000000 + 0 0x00010000>; + }; + }; +}; + +/include/ "fsl/p5020si-post.dtsi" diff --git a/arch/powerpc/platforms/85xx/corenet_generic.c b/arch/powerpc/platforms/85xx/corenet_generic.c index b395571..76e521e 100644 --- a/arch/powerpc/platforms/85xx/corenet_generic.c +++ b/arch/powerpc/platforms/85xx/corenet_generic.c @@ -161,6 +161,7 @@ static const char * const boards[] __initconst = { "fsl,T1042RDB", "fsl,T1042RDB_PI", "keymile,kmcoge4", + "varisys,CYRUS", NULL };
This board uses a P5020 chip, and boots just fine using the corenet_generic code. The device tree is very similar to the P5020DS, except that there is no Flash memory. The environment is, instead, stored on an MMC card on the motherboard. Signed-off-by: Andy Fleming <afleming@gmail.com> --- v2: Moved dts to cyrus_p5020.dts so we can add a p5040 version later Corrected the model/compatible to varisys,CYRUS arch/powerpc/boot/dts/cyrus_p5020.dts | 155 ++++++++++++++++++++++++++ arch/powerpc/platforms/85xx/corenet_generic.c | 1 + 2 files changed, 156 insertions(+) create mode 100644 arch/powerpc/boot/dts/cyrus_p5020.dts