diff mbox

[2/3] devicetree:bindings: add devicetree bindings for Freescale AHCI

Message ID 1441614196-4284-2-git-send-email-Yuantian.Tang@freescale.com
State Under Review, archived
Headers show

Commit Message

tang yuantian Sept. 7, 2015, 8:23 a.m. UTC
From: Tang Yuantian <Yuantian.Tang@freescale.com>

adds bindings for Freescale QorIQ AHCI SATA controller.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
---
 .../devicetree/bindings/ata/ahci-fsl-qoriq.txt      | 21 +++++++++++++++++++++
 1 file changed, 21 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt

Comments

Yang Li Sept. 9, 2015, 11:19 p.m. UTC | #1
On Mon, Sep 7, 2015 at 3:23 AM,  <Yuantian.Tang@freescale.com> wrote:
> From: Tang Yuantian <Yuantian.Tang@freescale.com>
>
> adds bindings for Freescale QorIQ AHCI SATA controller.
>
> Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
> ---
>  .../devicetree/bindings/ata/ahci-fsl-qoriq.txt      | 21 +++++++++++++++++++++
>  1 file changed, 21 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
>
> diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
> new file mode 100644
> index 0000000..b614e3b
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
> @@ -0,0 +1,21 @@
> +Binding for Freescale QorIQ AHCI SATA Controller
> +
> +Required properties:
> +  - reg: Physical base address and size of the controller's register area.
> +  - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
> +    chip could be ls1021a, ls2085a, ls1043a etc.
> +  - clocks: Input clock specifier. Refer to common clock bindings.
> +  - interrupts: Interrupt specifier. Refer to interrupt binding.
> +
> +Optional properties:
> +  - dma-coherent: Enable ACHI coherency DMA operation.
> +  - reg-names: register area names when there are more then 1 regster area.

A few typos here:
s/ACHI/AHCI/
s/coherency/coherent/
s/then/than/
s/regster/register/

Regards,
Leo
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tang yuantian Sept. 10, 2015, 1:23 a.m. UTC | #2
> -----Original Message-----

> From: pku.leo@gmail.com [mailto:pku.leo@gmail.com] On Behalf Of Li Yang

> Sent: Thursday, September 10, 2015 7:19 AM

> To: Tang Yuantian-B29983 <Yuantian.Tang@freescale.com>

> Cc: Hans de Goede <hdegoede@redhat.com>; tj@kernel.org; linux-

> ide@vger.kernel.org; lkml <linux-kernel@vger.kernel.org>;

> devicetree@vger.kernel.org

> Subject: Re: [PATCH 2/3] devicetree:bindings: add devicetree bindings for

> Freescale AHCI

> 

> On Mon, Sep 7, 2015 at 3:23 AM,  <Yuantian.Tang@freescale.com> wrote:

> > From: Tang Yuantian <Yuantian.Tang@freescale.com>

> >

> > adds bindings for Freescale QorIQ AHCI SATA controller.

> >

> > Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>

> > ---

> >  .../devicetree/bindings/ata/ahci-fsl-qoriq.txt      | 21

> +++++++++++++++++++++

> >  1 file changed, 21 insertions(+)

> >  create mode 100644 Documentation/devicetree/bindings/ata/ahci-fsl-

> qoriq.txt

> >

> > diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt

> b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt

> > new file mode 100644

> > index 0000000..b614e3b

> > --- /dev/null

> > +++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt

> > @@ -0,0 +1,21 @@

> > +Binding for Freescale QorIQ AHCI SATA Controller

> > +

> > +Required properties:

> > +  - reg: Physical base address and size of the controller's register area.

> > +  - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where

> > +    chip could be ls1021a, ls2085a, ls1043a etc.

> > +  - clocks: Input clock specifier. Refer to common clock bindings.

> > +  - interrupts: Interrupt specifier. Refer to interrupt binding.

> > +

> > +Optional properties:

> > +  - dma-coherent: Enable ACHI coherency DMA operation.

> > +  - reg-names: register area names when there are more then 1 regster

> area.

> 

> A few typos here:

> s/ACHI/AHCI/

> s/coherency/coherent/

> s/then/than/

> s/regster/register/

> 

Can't believe there is so many typos. Will fixed in follow-up patch.

Thanks,
Yuantian
> Regards,

> Leo
diff mbox

Patch

diff --git a/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
new file mode 100644
index 0000000..b614e3b
--- /dev/null
+++ b/Documentation/devicetree/bindings/ata/ahci-fsl-qoriq.txt
@@ -0,0 +1,21 @@ 
+Binding for Freescale QorIQ AHCI SATA Controller
+
+Required properties:
+  - reg: Physical base address and size of the controller's register area.
+  - compatible: Compatibility string. Must be 'fsl,<chip>-ahci', where
+    chip could be ls1021a, ls2085a, ls1043a etc.
+  - clocks: Input clock specifier. Refer to common clock bindings.
+  - interrupts: Interrupt specifier. Refer to interrupt binding.
+
+Optional properties:
+  - dma-coherent: Enable ACHI coherency DMA operation.
+  - reg-names: register area names when there are more then 1 regster area.
+
+Examples:
+	sata@3200000 {
+		compatible = "fsl,ls1021a-ahci";
+		reg = <0x0 0x3200000 0x0 0x10000>;
+		interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&platform_clk 1>;
+		dma-coherent;
+	};