diff mbox

[V11,01/27] acpi: split out pc smbus routines from acpi.c into pc_smbus.c

Message ID 1262672870-22607-2-git-send-email-yamahata@valinux.co.jp
State New
Headers show

Commit Message

Isaku Yamahata Jan. 5, 2010, 6:27 a.m. UTC 
Split out pc smbus routines from acpi.c into pc_smbus.c and
use it.
The split out smbus emulation will be used later.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>

---
changes v10 -> v11
- add DeviceState *qdev argument to pc_smbus_init()
  for info qtree.
---
 Makefile.target |    2 +
 hw/acpi.c       |  164 +++------------------------------------------------
 hw/pc_smbus.c   |  178 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
 hw/pc_smbus.h   |   21 +++++++
 4 files changed, 209 insertions(+), 156 deletions(-)
 create mode 100644 hw/pc_smbus.c
 create mode 100644 hw/pc_smbus.h

Comments

Aurelien Jarno Jan. 5, 2010, 10:11 p.m. UTC | #1 
On Tue, Jan 05, 2010 at 03:27:24PM +0900, Isaku Yamahata wrote:
> Split out pc smbus routines from acpi.c into pc_smbus.c and
> use it.

Given the code is not specific to PC, but is also used on MIPS, I am not
sure pc_smbus is the best name.

> The split out smbus emulation will be used later.
>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> 
> ---
> changes v10 -> v11
> - add DeviceState *qdev argument to pc_smbus_init()
>   for info qtree.
> ---
>  Makefile.target |    2 +
>  hw/acpi.c       |  164 +++------------------------------------------------
>  hw/pc_smbus.c   |  178 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  hw/pc_smbus.h   |   21 +++++++
>  4 files changed, 209 insertions(+), 156 deletions(-)
>  create mode 100644 hw/pc_smbus.c
>  create mode 100644 hw/pc_smbus.h
> 
> diff --git a/Makefile.target b/Makefile.target
> index 7c1f30c..2cde15f 100644
> --- a/Makefile.target
> +++ b/Makefile.target
> @@ -195,6 +195,7 @@ obj-i386-y += cirrus_vga.o apic.o ioapic.o parallel.o acpi.o piix_pci.o
>  obj-i386-y += usb-uhci.o vmmouse.o vmport.o vmware_vga.o hpet.o
>  obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o wdt_ib700.o
>  obj-i386-y += ne2000-isa.o
> +obj-i386-y += pc_smbus.o
>  
>  # shared objects
>  obj-ppc-y = ppc.o ide/core.o ide/qdev.o ide/isa.o ide/pci.o ide/macio.o
> @@ -225,6 +226,7 @@ obj-mips-y += ide/core.o ide/qdev.o ide/isa.o ide/pci.o ide/piix.o
>  obj-mips-y += gt64xxx.o pckbd.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
>  obj-mips-y += piix4.o parallel.o cirrus_vga.o pcspk.o $(sound-obj-y)
>  obj-mips-y += mipsnet.o ne2000-isa.o
> +obj-mips-y += pc_smbus.o
>  obj-mips-y += pflash_cfi01.o
>  obj-mips-y += vmware_vga.o
>  
> diff --git a/hw/acpi.c b/hw/acpi.c
> index 9a69e7d..507b308 100644
> --- a/hw/acpi.c
> +++ b/hw/acpi.c
> @@ -17,6 +17,7 @@
>   */
>  #include "hw.h"
>  #include "pc.h"
> +#include "pc_smbus.h"
>  #include "pci.h"
>  #include "qemu-timer.h"
>  #include "sysemu.h"
> @@ -40,15 +41,9 @@ typedef struct PIIX4PMState {
>      uint8_t apms;
>      QEMUTimer *tmr_timer;
>      int64_t tmr_overflow_time;
> -    i2c_bus *smbus;
> -    uint8_t smb_stat;
> -    uint8_t smb_ctl;
> -    uint8_t smb_cmd;
> -    uint8_t smb_addr;
> -    uint8_t smb_data0;
> -    uint8_t smb_data1;
> -    uint8_t smb_data[32];
> -    uint8_t smb_index;
> +
> +    PCSMBus smb;
> +
>      qemu_irq irq;
>  } PIIX4PMState;
>  
> @@ -66,14 +61,6 @@ typedef struct PIIX4PMState {
>  #define ACPI_ENABLE 0xf1
>  #define ACPI_DISABLE 0xf0
>  
> -#define SMBHSTSTS 0x00
> -#define SMBHSTCNT 0x02
> -#define SMBHSTCMD 0x03
> -#define SMBHSTADD 0x04
> -#define SMBHSTDAT0 0x05
> -#define SMBHSTDAT1 0x06
> -#define SMBBLKDAT 0x07
> -
>  static PIIX4PMState *pm_state;
>  
>  static uint32_t get_pmtmr(PIIX4PMState *s)
> @@ -279,141 +266,6 @@ static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
>  #endif
>  }
>  
> -static void smb_transaction(PIIX4PMState *s)
> -{
> -    uint8_t prot = (s->smb_ctl >> 2) & 0x07;
> -    uint8_t read = s->smb_addr & 0x01;
> -    uint8_t cmd = s->smb_cmd;
> -    uint8_t addr = s->smb_addr >> 1;
> -    i2c_bus *bus = s->smbus;
> -
> -#ifdef DEBUG
> -    printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
> -#endif
> -    switch(prot) {
> -    case 0x0:
> -        smbus_quick_command(bus, addr, read);
> -        break;
> -    case 0x1:
> -        if (read) {
> -            s->smb_data0 = smbus_receive_byte(bus, addr);
> -        } else {
> -            smbus_send_byte(bus, addr, cmd);
> -        }
> -        break;
> -    case 0x2:
> -        if (read) {
> -            s->smb_data0 = smbus_read_byte(bus, addr, cmd);
> -        } else {
> -            smbus_write_byte(bus, addr, cmd, s->smb_data0);
> -        }
> -        break;
> -    case 0x3:
> -        if (read) {
> -            uint16_t val;
> -            val = smbus_read_word(bus, addr, cmd);
> -            s->smb_data0 = val;
> -            s->smb_data1 = val >> 8;
> -        } else {
> -            smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
> -        }
> -        break;
> -    case 0x5:
> -        if (read) {
> -            s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
> -        } else {
> -            smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
> -        }
> -        break;
> -    default:
> -        goto error;
> -    }
> -    return;
> -
> -  error:
> -    s->smb_stat |= 0x04;
> -}
> -
> -static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
> -{
> -    PIIX4PMState *s = opaque;
> -    addr &= 0x3f;
> -#ifdef DEBUG
> -    printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
> -#endif
> -    switch(addr) {
> -    case SMBHSTSTS:
> -        s->smb_stat = 0;
> -        s->smb_index = 0;
> -        break;
> -    case SMBHSTCNT:
> -        s->smb_ctl = val;
> -        if (val & 0x40)
> -            smb_transaction(s);
> -        break;
> -    case SMBHSTCMD:
> -        s->smb_cmd = val;
> -        break;
> -    case SMBHSTADD:
> -        s->smb_addr = val;
> -        break;
> -    case SMBHSTDAT0:
> -        s->smb_data0 = val;
> -        break;
> -    case SMBHSTDAT1:
> -        s->smb_data1 = val;
> -        break;
> -    case SMBBLKDAT:
> -        s->smb_data[s->smb_index++] = val;
> -        if (s->smb_index > 31)
> -            s->smb_index = 0;
> -        break;
> -    default:
> -        break;
> -    }
> -}
> -
> -static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
> -{
> -    PIIX4PMState *s = opaque;
> -    uint32_t val;
> -
> -    addr &= 0x3f;
> -    switch(addr) {
> -    case SMBHSTSTS:
> -        val = s->smb_stat;
> -        break;
> -    case SMBHSTCNT:
> -        s->smb_index = 0;
> -        val = s->smb_ctl & 0x1f;
> -        break;
> -    case SMBHSTCMD:
> -        val = s->smb_cmd;
> -        break;
> -    case SMBHSTADD:
> -        val = s->smb_addr;
> -        break;
> -    case SMBHSTDAT0:
> -        val = s->smb_data0;
> -        break;
> -    case SMBHSTDAT1:
> -        val = s->smb_data1;
> -        break;
> -    case SMBBLKDAT:
> -        val = s->smb_data[s->smb_index++];
> -        if (s->smb_index > 31)
> -            s->smb_index = 0;
> -        break;
> -    default:
> -        val = 0;
> -        break;
> -    }
> -#ifdef DEBUG
> -    printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
> -#endif
> -    return val;
> -}
> -
>  static void pm_io_space_update(PIIX4PMState *s)
>  {
>      uint32_t pm_io_base;
> @@ -542,8 +394,8 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>      pci_conf[0x90] = smb_io_base | 1;
>      pci_conf[0x91] = smb_io_base >> 8;
>      pci_conf[0xd2] = 0x09;
> -    register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
> -    register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
> +    register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
> +    register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
>  
>      s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
>  
> @@ -551,11 +403,11 @@ i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
>  
>      vmstate_register(0, &vmstate_acpi, s);
>  
> -    s->smbus = i2c_init_bus(NULL, "i2c");
> +    pc_smbus_init(NULL, &s->smb);
>      s->irq = sci_irq;
>      qemu_register_reset(piix4_reset, s);
>  
> -    return s->smbus;
> +    return s->smb.smbus;
>  }
>  
>  #define GPE_BASE 0xafe0
> diff --git a/hw/pc_smbus.c b/hw/pc_smbus.c
> new file mode 100644
> index 0000000..30cdaa7
> --- /dev/null
> +++ b/hw/pc_smbus.c
> @@ -0,0 +1,178 @@
> +/*
> + * PC SMBus implementation
> + * splitted from acpi.c
> + *
> + * Copyright (c) 2006 Fabrice Bellard
> + *
> + * This library is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU Lesser General Public
> + * License version 2 as published by the Free Software Foundation.
> + *
> + * This library is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
> + * Lesser General Public License for more details.
> + *
> + * You should have received a copy of the GNU Lesser General Public
> + * License along with this library; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
> + */
> +#include "hw.h"
> +#include "pc.h"
> +#include "pc_smbus.h"
> +#include "pci.h"
> +#include "qemu-timer.h"
> +#include "sysemu.h"
> +#include "i2c.h"
> +#include "smbus.h"
> +#include "kvm.h"

Do we really need kvm.h here?

> +
> +/* no save/load? */
> +
> +#define SMBHSTSTS       0x00
> +#define SMBHSTCNT       0x02
> +#define SMBHSTCMD       0x03
> +#define SMBHSTADD       0x04
> +#define SMBHSTDAT0      0x05
> +#define SMBHSTDAT1      0x06
> +#define SMBBLKDAT       0x07
> +
> +static void smb_transaction(PCSMBus *s)
> +{
> +    uint8_t prot = (s->smb_ctl >> 2) & 0x07;
> +    uint8_t read = s->smb_addr & 0x01;
> +    uint8_t cmd = s->smb_cmd;
> +    uint8_t addr = s->smb_addr >> 1;
> +    i2c_bus *bus = s->smbus;
> +
> +#ifdef DEBUG
> +    printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
> +#endif
> +    switch(prot) {
> +    case 0x0:
> +        smbus_quick_command(bus, addr, read);
> +        break;
> +    case 0x1:
> +        if (read) {
> +            s->smb_data0 = smbus_receive_byte(bus, addr);
> +        } else {
> +            smbus_send_byte(bus, addr, cmd);
> +        }
> +        break;
> +    case 0x2:
> +        if (read) {
> +            s->smb_data0 = smbus_read_byte(bus, addr, cmd);
> +        } else {
> +            smbus_write_byte(bus, addr, cmd, s->smb_data0);
> +        }
> +        break;
> +    case 0x3:
> +        if (read) {
> +            uint16_t val;
> +            val = smbus_read_word(bus, addr, cmd);
> +            s->smb_data0 = val;
> +            s->smb_data1 = val >> 8;
> +        } else {
> +            smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
> +        }
> +        break;
> +    case 0x5:
> +        if (read) {
> +            s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
> +        } else {
> +            smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
> +        }
> +        break;
> +    default:
> +        goto error;
> +    }
> +    return;
> +
> +  error:
> +    s->smb_stat |= 0x04;
> +}
> +
> +void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
> +{
> +    PCSMBus *s = opaque;
> +    addr &= 0x3f;
> +#ifdef DEBUG
> +    printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
> +#endif
> +    switch(addr) {
> +    case SMBHSTSTS:
> +        s->smb_stat = 0;
> +        s->smb_index = 0;
> +        break;
> +    case SMBHSTCNT:
> +        s->smb_ctl = val;
> +        if (val & 0x40)
> +            smb_transaction(s);
> +        break;
> +    case SMBHSTCMD:
> +        s->smb_cmd = val;
> +        break;
> +    case SMBHSTADD:
> +        s->smb_addr = val;
> +        break;
> +    case SMBHSTDAT0:
> +        s->smb_data0 = val;
> +        break;
> +    case SMBHSTDAT1:
> +        s->smb_data1 = val;
> +        break;
> +    case SMBBLKDAT:
> +        s->smb_data[s->smb_index++] = val;
> +        if (s->smb_index > 31)
> +            s->smb_index = 0;
> +        break;
> +    default:
> +        break;
> +    }
> +}
> +
> +uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
> +{
> +    PCSMBus *s = opaque;
> +    uint32_t val;
> +
> +    addr &= 0x3f;
> +    switch(addr) {
> +    case SMBHSTSTS:
> +        val = s->smb_stat;
> +        break;
> +    case SMBHSTCNT:
> +        s->smb_index = 0;
> +        val = s->smb_ctl & 0x1f;
> +        break;
> +    case SMBHSTCMD:
> +        val = s->smb_cmd;
> +        break;
> +    case SMBHSTADD:
> +        val = s->smb_addr;
> +        break;
> +    case SMBHSTDAT0:
> +        val = s->smb_data0;
> +        break;
> +    case SMBHSTDAT1:
> +        val = s->smb_data1;
> +        break;
> +    case SMBBLKDAT:
> +        val = s->smb_data[s->smb_index++];
> +        if (s->smb_index > 31)
> +            s->smb_index = 0;
> +        break;
> +    default:
> +        val = 0;
> +        break;
> +    }
> +#ifdef DEBUG
> +    printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
> +#endif
> +    return val;
> +}
> +
> +void pc_smbus_init(DeviceState *parent, PCSMBus *smb)
> +{
> +    smb->smbus = i2c_init_bus(parent, "i2c");
> +}
> diff --git a/hw/pc_smbus.h b/hw/pc_smbus.h
> new file mode 100644
> index 0000000..27c0eec
> --- /dev/null
> +++ b/hw/pc_smbus.h
> @@ -0,0 +1,21 @@
> +#ifndef PC_SMBUS_H
> +#define PC_SMBUS_H
> +
> +typedef struct PCSMBus {
> +    i2c_bus *smbus;
> +
> +    uint8_t smb_stat;
> +    uint8_t smb_ctl;
> +    uint8_t smb_cmd;
> +    uint8_t smb_addr;
> +    uint8_t smb_data0;
> +    uint8_t smb_data1;
> +    uint8_t smb_data[32];
> +    uint8_t smb_index;
> +} PCSMBus;
> +
> +void pc_smbus_init(DeviceState *parent, PCSMBus *smb);
> +void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val);
> +uint32_t smb_ioport_readb(void *opaque, uint32_t addr);
> +
> +#endif /* !PC_SMBUS_H */
> -- 
> 1.6.5.4
> 
> 
> 
>
Isaku Yamahata Jan. 6, 2010, 1:24 a.m. UTC | #2 
On Tue, Jan 05, 2010 at 11:11:00PM +0100, Aurelien Jarno wrote:
> On Tue, Jan 05, 2010 at 03:27:24PM +0900, Isaku Yamahata wrote:
> > Split out pc smbus routines from acpi.c into pc_smbus.c and
> > use it.
> 
> Given the code is not specific to PC, but is also used on MIPS, I am not
> sure pc_smbus is the best name.

Okay. I'll drop pc_ prefix. (for both file name and function names).
Do you also want similar to pc_apm.c in the next patch?
Aurelien Jarno Jan. 6, 2010, 7:26 a.m. UTC | #3 
Isaku Yamahata a écrit :
> On Tue, Jan 05, 2010 at 11:11:00PM +0100, Aurelien Jarno wrote:
>> On Tue, Jan 05, 2010 at 03:27:24PM +0900, Isaku Yamahata wrote:
>>> Split out pc smbus routines from acpi.c into pc_smbus.c and
>>> use it.
>> Given the code is not specific to PC, but is also used on MIPS, I am not
>> sure pc_smbus is the best name.
> 
> Okay. I'll drop pc_ prefix. (for both file name and function names).
> Do you also want similar to pc_apm.c in the next patch?
> 

Yes, it looks better to me.
diff mbox

Patch

diff --git a/Makefile.target b/Makefile.target
index 7c1f30c..2cde15f 100644
--- a/Makefile.target
+++ b/Makefile.target
@@ -195,6 +195,7 @@  obj-i386-y += cirrus_vga.o apic.o ioapic.o parallel.o acpi.o piix_pci.o
 obj-i386-y += usb-uhci.o vmmouse.o vmport.o vmware_vga.o hpet.o
 obj-i386-y += device-hotplug.o pci-hotplug.o smbios.o wdt_ib700.o
 obj-i386-y += ne2000-isa.o
+obj-i386-y += pc_smbus.o
 
 # shared objects
 obj-ppc-y = ppc.o ide/core.o ide/qdev.o ide/isa.o ide/pci.o ide/macio.o
@@ -225,6 +226,7 @@  obj-mips-y += ide/core.o ide/qdev.o ide/isa.o ide/pci.o ide/piix.o
 obj-mips-y += gt64xxx.o pckbd.o fdc.o mc146818rtc.o usb-uhci.o acpi.o ds1225y.o
 obj-mips-y += piix4.o parallel.o cirrus_vga.o pcspk.o $(sound-obj-y)
 obj-mips-y += mipsnet.o ne2000-isa.o
+obj-mips-y += pc_smbus.o
 obj-mips-y += pflash_cfi01.o
 obj-mips-y += vmware_vga.o
 
diff --git a/hw/acpi.c b/hw/acpi.c
index 9a69e7d..507b308 100644
--- a/hw/acpi.c
+++ b/hw/acpi.c
@@ -17,6 +17,7 @@ 
  */
 #include "hw.h"
 #include "pc.h"
+#include "pc_smbus.h"
 #include "pci.h"
 #include "qemu-timer.h"
 #include "sysemu.h"
@@ -40,15 +41,9 @@  typedef struct PIIX4PMState {
     uint8_t apms;
     QEMUTimer *tmr_timer;
     int64_t tmr_overflow_time;
-    i2c_bus *smbus;
-    uint8_t smb_stat;
-    uint8_t smb_ctl;
-    uint8_t smb_cmd;
-    uint8_t smb_addr;
-    uint8_t smb_data0;
-    uint8_t smb_data1;
-    uint8_t smb_data[32];
-    uint8_t smb_index;
+
+    PCSMBus smb;
+
     qemu_irq irq;
 } PIIX4PMState;
 
@@ -66,14 +61,6 @@  typedef struct PIIX4PMState {
 #define ACPI_ENABLE 0xf1
 #define ACPI_DISABLE 0xf0
 
-#define SMBHSTSTS 0x00
-#define SMBHSTCNT 0x02
-#define SMBHSTCMD 0x03
-#define SMBHSTADD 0x04
-#define SMBHSTDAT0 0x05
-#define SMBHSTDAT1 0x06
-#define SMBBLKDAT 0x07
-
 static PIIX4PMState *pm_state;
 
 static uint32_t get_pmtmr(PIIX4PMState *s)
@@ -279,141 +266,6 @@  static void acpi_dbg_writel(void *opaque, uint32_t addr, uint32_t val)
 #endif
 }
 
-static void smb_transaction(PIIX4PMState *s)
-{
-    uint8_t prot = (s->smb_ctl >> 2) & 0x07;
-    uint8_t read = s->smb_addr & 0x01;
-    uint8_t cmd = s->smb_cmd;
-    uint8_t addr = s->smb_addr >> 1;
-    i2c_bus *bus = s->smbus;
-
-#ifdef DEBUG
-    printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
-#endif
-    switch(prot) {
-    case 0x0:
-        smbus_quick_command(bus, addr, read);
-        break;
-    case 0x1:
-        if (read) {
-            s->smb_data0 = smbus_receive_byte(bus, addr);
-        } else {
-            smbus_send_byte(bus, addr, cmd);
-        }
-        break;
-    case 0x2:
-        if (read) {
-            s->smb_data0 = smbus_read_byte(bus, addr, cmd);
-        } else {
-            smbus_write_byte(bus, addr, cmd, s->smb_data0);
-        }
-        break;
-    case 0x3:
-        if (read) {
-            uint16_t val;
-            val = smbus_read_word(bus, addr, cmd);
-            s->smb_data0 = val;
-            s->smb_data1 = val >> 8;
-        } else {
-            smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
-        }
-        break;
-    case 0x5:
-        if (read) {
-            s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
-        } else {
-            smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
-        }
-        break;
-    default:
-        goto error;
-    }
-    return;
-
-  error:
-    s->smb_stat |= 0x04;
-}
-
-static void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
-{
-    PIIX4PMState *s = opaque;
-    addr &= 0x3f;
-#ifdef DEBUG
-    printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
-#endif
-    switch(addr) {
-    case SMBHSTSTS:
-        s->smb_stat = 0;
-        s->smb_index = 0;
-        break;
-    case SMBHSTCNT:
-        s->smb_ctl = val;
-        if (val & 0x40)
-            smb_transaction(s);
-        break;
-    case SMBHSTCMD:
-        s->smb_cmd = val;
-        break;
-    case SMBHSTADD:
-        s->smb_addr = val;
-        break;
-    case SMBHSTDAT0:
-        s->smb_data0 = val;
-        break;
-    case SMBHSTDAT1:
-        s->smb_data1 = val;
-        break;
-    case SMBBLKDAT:
-        s->smb_data[s->smb_index++] = val;
-        if (s->smb_index > 31)
-            s->smb_index = 0;
-        break;
-    default:
-        break;
-    }
-}
-
-static uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
-{
-    PIIX4PMState *s = opaque;
-    uint32_t val;
-
-    addr &= 0x3f;
-    switch(addr) {
-    case SMBHSTSTS:
-        val = s->smb_stat;
-        break;
-    case SMBHSTCNT:
-        s->smb_index = 0;
-        val = s->smb_ctl & 0x1f;
-        break;
-    case SMBHSTCMD:
-        val = s->smb_cmd;
-        break;
-    case SMBHSTADD:
-        val = s->smb_addr;
-        break;
-    case SMBHSTDAT0:
-        val = s->smb_data0;
-        break;
-    case SMBHSTDAT1:
-        val = s->smb_data1;
-        break;
-    case SMBBLKDAT:
-        val = s->smb_data[s->smb_index++];
-        if (s->smb_index > 31)
-            s->smb_index = 0;
-        break;
-    default:
-        val = 0;
-        break;
-    }
-#ifdef DEBUG
-    printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
-#endif
-    return val;
-}
-
 static void pm_io_space_update(PIIX4PMState *s)
 {
     uint32_t pm_io_base;
@@ -542,8 +394,8 @@  i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
     pci_conf[0x90] = smb_io_base | 1;
     pci_conf[0x91] = smb_io_base >> 8;
     pci_conf[0xd2] = 0x09;
-    register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, s);
-    register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, s);
+    register_ioport_write(smb_io_base, 64, 1, smb_ioport_writeb, &s->smb);
+    register_ioport_read(smb_io_base, 64, 1, smb_ioport_readb, &s->smb);
 
     s->tmr_timer = qemu_new_timer(vm_clock, pm_tmr_timer, s);
 
@@ -551,11 +403,11 @@  i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 
     vmstate_register(0, &vmstate_acpi, s);
 
-    s->smbus = i2c_init_bus(NULL, "i2c");
+    pc_smbus_init(NULL, &s->smb);
     s->irq = sci_irq;
     qemu_register_reset(piix4_reset, s);
 
-    return s->smbus;
+    return s->smb.smbus;
 }
 
 #define GPE_BASE 0xafe0
diff --git a/hw/pc_smbus.c b/hw/pc_smbus.c
new file mode 100644
index 0000000..30cdaa7
--- /dev/null
+++ b/hw/pc_smbus.c
@@ -0,0 +1,178 @@ 
+/*
+ * PC SMBus implementation
+ * splitted from acpi.c
+ *
+ * Copyright (c) 2006 Fabrice Bellard
+ *
+ * This library is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU Lesser General Public
+ * License version 2 as published by the Free Software Foundation.
+ *
+ * This library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ * Lesser General Public License for more details.
+ *
+ * You should have received a copy of the GNU Lesser General Public
+ * License along with this library; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin Street, Fifth Floor, Boston MA  02110-1301 USA
+ */
+#include "hw.h"
+#include "pc.h"
+#include "pc_smbus.h"
+#include "pci.h"
+#include "qemu-timer.h"
+#include "sysemu.h"
+#include "i2c.h"
+#include "smbus.h"
+#include "kvm.h"
+
+/* no save/load? */
+
+#define SMBHSTSTS       0x00
+#define SMBHSTCNT       0x02
+#define SMBHSTCMD       0x03
+#define SMBHSTADD       0x04
+#define SMBHSTDAT0      0x05
+#define SMBHSTDAT1      0x06
+#define SMBBLKDAT       0x07
+
+static void smb_transaction(PCSMBus *s)
+{
+    uint8_t prot = (s->smb_ctl >> 2) & 0x07;
+    uint8_t read = s->smb_addr & 0x01;
+    uint8_t cmd = s->smb_cmd;
+    uint8_t addr = s->smb_addr >> 1;
+    i2c_bus *bus = s->smbus;
+
+#ifdef DEBUG
+    printf("SMBus trans addr=0x%02x prot=0x%02x\n", addr, prot);
+#endif
+    switch(prot) {
+    case 0x0:
+        smbus_quick_command(bus, addr, read);
+        break;
+    case 0x1:
+        if (read) {
+            s->smb_data0 = smbus_receive_byte(bus, addr);
+        } else {
+            smbus_send_byte(bus, addr, cmd);
+        }
+        break;
+    case 0x2:
+        if (read) {
+            s->smb_data0 = smbus_read_byte(bus, addr, cmd);
+        } else {
+            smbus_write_byte(bus, addr, cmd, s->smb_data0);
+        }
+        break;
+    case 0x3:
+        if (read) {
+            uint16_t val;
+            val = smbus_read_word(bus, addr, cmd);
+            s->smb_data0 = val;
+            s->smb_data1 = val >> 8;
+        } else {
+            smbus_write_word(bus, addr, cmd, (s->smb_data1 << 8) | s->smb_data0);
+        }
+        break;
+    case 0x5:
+        if (read) {
+            s->smb_data0 = smbus_read_block(bus, addr, cmd, s->smb_data);
+        } else {
+            smbus_write_block(bus, addr, cmd, s->smb_data, s->smb_data0);
+        }
+        break;
+    default:
+        goto error;
+    }
+    return;
+
+  error:
+    s->smb_stat |= 0x04;
+}
+
+void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val)
+{
+    PCSMBus *s = opaque;
+    addr &= 0x3f;
+#ifdef DEBUG
+    printf("SMB writeb port=0x%04x val=0x%02x\n", addr, val);
+#endif
+    switch(addr) {
+    case SMBHSTSTS:
+        s->smb_stat = 0;
+        s->smb_index = 0;
+        break;
+    case SMBHSTCNT:
+        s->smb_ctl = val;
+        if (val & 0x40)
+            smb_transaction(s);
+        break;
+    case SMBHSTCMD:
+        s->smb_cmd = val;
+        break;
+    case SMBHSTADD:
+        s->smb_addr = val;
+        break;
+    case SMBHSTDAT0:
+        s->smb_data0 = val;
+        break;
+    case SMBHSTDAT1:
+        s->smb_data1 = val;
+        break;
+    case SMBBLKDAT:
+        s->smb_data[s->smb_index++] = val;
+        if (s->smb_index > 31)
+            s->smb_index = 0;
+        break;
+    default:
+        break;
+    }
+}
+
+uint32_t smb_ioport_readb(void *opaque, uint32_t addr)
+{
+    PCSMBus *s = opaque;
+    uint32_t val;
+
+    addr &= 0x3f;
+    switch(addr) {
+    case SMBHSTSTS:
+        val = s->smb_stat;
+        break;
+    case SMBHSTCNT:
+        s->smb_index = 0;
+        val = s->smb_ctl & 0x1f;
+        break;
+    case SMBHSTCMD:
+        val = s->smb_cmd;
+        break;
+    case SMBHSTADD:
+        val = s->smb_addr;
+        break;
+    case SMBHSTDAT0:
+        val = s->smb_data0;
+        break;
+    case SMBHSTDAT1:
+        val = s->smb_data1;
+        break;
+    case SMBBLKDAT:
+        val = s->smb_data[s->smb_index++];
+        if (s->smb_index > 31)
+            s->smb_index = 0;
+        break;
+    default:
+        val = 0;
+        break;
+    }
+#ifdef DEBUG
+    printf("SMB readb port=0x%04x val=0x%02x\n", addr, val);
+#endif
+    return val;
+}
+
+void pc_smbus_init(DeviceState *parent, PCSMBus *smb)
+{
+    smb->smbus = i2c_init_bus(parent, "i2c");
+}
diff --git a/hw/pc_smbus.h b/hw/pc_smbus.h
new file mode 100644
index 0000000..27c0eec
--- /dev/null
+++ b/hw/pc_smbus.h
@@ -0,0 +1,21 @@ 
+#ifndef PC_SMBUS_H
+#define PC_SMBUS_H
+
+typedef struct PCSMBus {
+    i2c_bus *smbus;
+
+    uint8_t smb_stat;
+    uint8_t smb_ctl;
+    uint8_t smb_cmd;
+    uint8_t smb_addr;
+    uint8_t smb_data0;
+    uint8_t smb_data1;
+    uint8_t smb_data[32];
+    uint8_t smb_index;
+} PCSMBus;
+
+void pc_smbus_init(DeviceState *parent, PCSMBus *smb);
+void smb_ioport_writeb(void *opaque, uint32_t addr, uint32_t val);
+uint32_t smb_ioport_readb(void *opaque, uint32_t addr);
+
+#endif /* !PC_SMBUS_H */