{"id":4901,"url":"http://patchwork.ozlabs.org/api/series/4901/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/list/?series=4901","project":{"id":18,"url":"http://patchwork.ozlabs.org/api/projects/18/?format=json","name":"U-Boot","link_name":"uboot","list_id":"u-boot.lists.denx.de","list_email":"u-boot@lists.denx.de","web_url":null,"scm_url":null,"webscm_url":null,"list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"Add FPGA, SDRAM, SPL loads U-boot & booting to console","date":"2017-09-25T08:39:56","submitter":{"id":70549,"url":"http://patchwork.ozlabs.org/api/people/70549/?format=json","name":"Chee, Tien Fong","email":"tien.fong.chee@intel.com"},"version":2,"total":19,"received_total":19,"received_all":true,"mbox":"http://patchwork.ozlabs.org/series/4901/mbox/","cover_letter":{"id":818100,"url":"http://patchwork.ozlabs.org/api/covers/818100/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/cover/1506328815-23733-1-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-1-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:39:56","name":"[U-Boot,v2,00/19] Add FPGA, SDRAM, SPL loads U-boot & booting to console","mbox":"http://patchwork.ozlabs.org/project/uboot/cover/1506328815-23733-1-git-send-email-tien.fong.chee@intel.com/mbox/"},"patches":[{"id":818103,"url":"http://patchwork.ozlabs.org/api/patches/818103/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-2-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-2-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:39:57","name":"[U-Boot,v2,01/19] ARM: socfpga: add bindings doc for arria10 fpga manager","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-2-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818101,"url":"http://patchwork.ozlabs.org/api/patches/818101/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-3-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-3-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:39:58","name":"[U-Boot,v2,02/19] doc: dtbinding: Description on FPGA RBF properties at Arria 10 FPGA manager","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-3-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818108,"url":"http://patchwork.ozlabs.org/api/patches/818108/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-4-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-4-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:39:59","name":"[U-Boot,v2,03/19] dts: Add FPGA bitstream properties to Arria 10 DTS","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-4-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818102,"url":"http://patchwork.ozlabs.org/api/patches/818102/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-5-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-5-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:00","name":"[U-Boot,v2,04/19] arm: socfpga: Add Arria 10 SoCFPGA programming interface","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-5-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818105,"url":"http://patchwork.ozlabs.org/api/patches/818105/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-6-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-6-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:01","name":"[U-Boot,v2,05/19] arm: socfpga: Enhance FPGA program write rbf data with size >= 4 bytes","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-6-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818128,"url":"http://patchwork.ozlabs.org/api/patches/818128/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-7-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-7-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:02","name":"[U-Boot,v2,06/19] dts: Enable fpga-mgr node build for Arria 10 SPL","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-7-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818104,"url":"http://patchwork.ozlabs.org/api/patches/818104/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-8-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-8-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:03","name":"[U-Boot,v2,07/19] fdt: Add compatible strings for Arria 10","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-8-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818119,"url":"http://patchwork.ozlabs.org/api/patches/818119/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-9-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-9-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:04","name":"[U-Boot,v2,08/19] fs: Enable generic filesystems interface support in SPL.","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-9-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818131,"url":"http://patchwork.ozlabs.org/api/patches/818131/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-10-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-10-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:05","name":"[U-Boot,v2,09/19] arm: socfpga: Add drivers for programing FPGA from flash","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-10-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818110,"url":"http://patchwork.ozlabs.org/api/patches/818110/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-11-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-11-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:06","name":"[U-Boot,v2,10/19] arm: socfpga: Rename the gen5 sdram driver to more specific name","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-11-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818107,"url":"http://patchwork.ozlabs.org/api/patches/818107/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-12-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-12-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:07","name":"[U-Boot,v2,11/19] arm: socfpga: Add DRAM bank size initialization function","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-12-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818129,"url":"http://patchwork.ozlabs.org/api/patches/818129/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-13-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-13-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:08","name":"[U-Boot,v2,12/19] arm: socfpga: Add DDR driver for Arria 10","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-13-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818115,"url":"http://patchwork.ozlabs.org/api/patches/818115/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-14-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-14-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:09","name":"[U-Boot,v2,13/19] configs: Add DDR Kconfig support for Arria 10","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-14-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818112,"url":"http://patchwork.ozlabs.org/api/patches/818112/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-15-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-15-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:10","name":"[U-Boot,v2,14/19] arm: socfpga: Enable build for DDR Arria 10","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-15-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818118,"url":"http://patchwork.ozlabs.org/api/patches/818118/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-16-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-16-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:11","name":"[U-Boot,v2,15/19] arm: socfpga: Add support to memory allocation in SPL","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-16-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818120,"url":"http://patchwork.ozlabs.org/api/patches/818120/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-17-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-17-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:12","name":"[U-Boot,v2,16/19] arm: socfpga: Enhance Intel SoCFPGA program header to support Arria 10","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-17-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818130,"url":"http://patchwork.ozlabs.org/api/patches/818130/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-18-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-18-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:13","name":"[U-Boot,v2,17/19] arm: socfpga: Adding clock frequency info for U-boot","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-18-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818126,"url":"http://patchwork.ozlabs.org/api/patches/818126/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-19-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-19-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:14","name":"[U-Boot,v2,18/19] arm: socfpga: Adding SoCFPGA info for both SPL and U-boot","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-19-git-send-email-tien.fong.chee@intel.com/mbox/"},{"id":818109,"url":"http://patchwork.ozlabs.org/api/patches/818109/?format=json","web_url":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-20-git-send-email-tien.fong.chee@intel.com/","msgid":"<1506328815-23733-20-git-send-email-tien.fong.chee@intel.com>","list_archive_url":null,"date":"2017-09-25T08:40:15","name":"[U-Boot,v2,19/19] arm: socfpga: Enable SPL loading U-boot to DDR and booting U-boot","mbox":"http://patchwork.ozlabs.org/project/uboot/patch/1506328815-23733-20-git-send-email-tien.fong.chee@intel.com/mbox/"}]}