{"id":2751,"url":"http://patchwork.ozlabs.org/api/series/2751/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=2751","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"name":"ARMv8M: support security extn in the NVIC","date":"2017-09-12T18:13:53","submitter":{"id":5111,"url":"http://patchwork.ozlabs.org/api/people/5111/?format=json","name":"Peter Maydell","email":"peter.maydell@linaro.org"},"version":1,"total":19,"received_total":19,"received_all":true,"mbox":"http://patchwork.ozlabs.org/series/2751/mbox/","cover_letter":{"id":812988,"url":"http://patchwork.ozlabs.org/api/covers/812988/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/cover/1505240046-11454-1-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-1-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:47","name":"[00/19] ARMv8M: support security extn in the NVIC","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/cover/1505240046-11454-1-git-send-email-peter.maydell@linaro.org/mbox/"},"patches":[{"id":812998,"url":"http://patchwork.ozlabs.org/api/patches/812998/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-2-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-2-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:48","name":"[01/19] target/arm: Implement MSR/MRS access to NS banked registers","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-2-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":812987,"url":"http://patchwork.ozlabs.org/api/patches/812987/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-3-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-3-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:49","name":"[02/19] nvic: Add banked exception states","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-3-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":812992,"url":"http://patchwork.ozlabs.org/api/patches/812992/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-4-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-4-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:50","name":"[03/19] nvic: Add cached vectpending_is_s_banked state","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-4-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":812990,"url":"http://patchwork.ozlabs.org/api/patches/812990/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-5-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-5-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:51","name":"[04/19] nvic: Add cached vectpending_prio state","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-5-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":812993,"url":"http://patchwork.ozlabs.org/api/patches/812993/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-6-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-6-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:52","name":"[05/19] nvic: Implement AIRCR changes for v8M","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-6-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":812984,"url":"http://patchwork.ozlabs.org/api/patches/812984/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-7-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-7-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:53","name":"[06/19] nvic: Make ICSR.RETTOBASE handle banked exceptions","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-7-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":812986,"url":"http://patchwork.ozlabs.org/api/patches/812986/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-8-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-8-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:54","name":"[07/19] nvic: Implement NVIC_ITNS<n> registers","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-8-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":813000,"url":"http://patchwork.ozlabs.org/api/patches/813000/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-9-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-9-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:55","name":"[08/19] nvic: Handle banked exceptions in nvic_recompute_state()","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-9-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":812999,"url":"http://patchwork.ozlabs.org/api/patches/812999/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-10-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-10-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:56","name":"[09/19] nvic: Make set_pending and clear_pending take a secure parameter","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-10-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":813003,"url":"http://patchwork.ozlabs.org/api/patches/813003/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-11-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-11-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:57","name":"[10/19] nvic: Make SHPR registers banked","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-11-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":813001,"url":"http://patchwork.ozlabs.org/api/patches/813001/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-12-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-12-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:58","name":"[11/19] nvic: Compare group priority for escalation to HF","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-12-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":812997,"url":"http://patchwork.ozlabs.org/api/patches/812997/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-13-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-13-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:13:59","name":"[12/19] nvic: In escalation to HardFault, support HF not being priority -1","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-13-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":813004,"url":"http://patchwork.ozlabs.org/api/patches/813004/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-14-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-14-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:14:00","name":"[13/19] nvic: Implement v8M changes to fixed priority exceptions","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-14-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":812991,"url":"http://patchwork.ozlabs.org/api/patches/812991/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-15-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-15-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:14:01","name":"[14/19] nvic: Disable the non-secure HardFault if AIRCR.BFHFNMINS is clear","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-15-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":813005,"url":"http://patchwork.ozlabs.org/api/patches/813005/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-16-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-16-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:14:02","name":"[15/19] nvic: Handle v8M changes in nvic_exec_prio()","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-16-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":812994,"url":"http://patchwork.ozlabs.org/api/patches/812994/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-17-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-17-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:14:03","name":"[16/19] target/arm: Handle banking in negative-execution-priority check in cpu_mmu_index()","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-17-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":813006,"url":"http://patchwork.ozlabs.org/api/patches/813006/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-18-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-18-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:14:04","name":"[17/19] nvic: Make ICSR banked for v8M","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-18-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":813002,"url":"http://patchwork.ozlabs.org/api/patches/813002/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-19-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-19-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:14:05","name":"[18/19] nvic: Make SHCSR banked for v8M","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-19-git-send-email-peter.maydell@linaro.org/mbox/"},{"id":812995,"url":"http://patchwork.ozlabs.org/api/patches/812995/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-20-git-send-email-peter.maydell@linaro.org/","msgid":"<1505240046-11454-20-git-send-email-peter.maydell@linaro.org>","list_archive_url":null,"date":"2017-09-12T18:14:06","name":"[19/19] nvic: Support banked exceptions in acknowledge and complete","mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/1505240046-11454-20-git-send-email-peter.maydell@linaro.org/mbox/"}]}