{"id":856687,"url":"http://patchwork.ozlabs.org/api/patches/856687/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20180108024558.17983-15-f4bug@amsat.org/","project":{"id":14,"url":"http://patchwork.ozlabs.org/api/projects/14/?format=json","name":"QEMU Development","link_name":"qemu-devel","list_id":"qemu-devel.nongnu.org","list_email":"qemu-devel@nongnu.org","web_url":"","scm_url":"","webscm_url":"","list_archive_url":"","list_archive_url_format":"","commit_url_format":""},"msgid":"<20180108024558.17983-15-f4bug@amsat.org>","list_archive_url":null,"date":"2018-01-08T02:45:43","name":"[14/29] piix4: add Reset Control Register","commit_ref":null,"pull_url":null,"state":"new","archived":false,"hash":"486f17833d0ca5cb0df98718f1938f58bba2587f","submitter":{"id":70924,"url":"http://patchwork.ozlabs.org/api/people/70924/?format=json","name":"Philippe Mathieu-Daudé","email":"f4bug@amsat.org"},"delegate":null,"mbox":"http://patchwork.ozlabs.org/project/qemu-devel/patch/20180108024558.17983-15-f4bug@amsat.org/mbox/","series":[{"id":21847,"url":"http://patchwork.ozlabs.org/api/series/21847/?format=json","web_url":"http://patchwork.ozlabs.org/project/qemu-devel/list/?series=21847","date":"2018-01-08T02:45:30","name":"remove i386/pc dependency: generic SuperIO, PIIX cleanup","version":1,"mbox":"http://patchwork.ozlabs.org/series/21847/mbox/"}],"comments":"http://patchwork.ozlabs.org/api/patches/856687/comments/","check":"pending","checks":"http://patchwork.ozlabs.org/api/patches/856687/checks/","tags":{},"related":[],"headers":{"Return-Path":"","X-Original-To":"incoming@patchwork.ozlabs.org","Delivered-To":"patchwork-incoming@bilbo.ozlabs.org","Authentication-Results":["ozlabs.org;\n\tspf=pass (mailfrom) smtp.mailfrom=nongnu.org\n\t(client-ip=2001:4830:134:3::11; helo=lists.gnu.org;\n\tenvelope-from=qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org;\n\treceiver=)","ozlabs.org;\n\tdkim=fail reason=\"signature verification failed\" (2048-bit key;\n\tunprotected) header.d=gmail.com header.i=@gmail.com\n\theader.b=\"rMPM8bwn\"; dkim-atps=neutral"],"Received":["from lists.gnu.org (lists.gnu.org [IPv6:2001:4830:134:3::11])\n\t(using TLSv1 with cipher AES256-SHA (256/256 bits))\n\t(No client certificate requested)\n\tby ozlabs.org (Postfix) with ESMTPS id 3zFKw01738z9s7n\n\tfor ;\n\tMon, 8 Jan 2018 14:07:58 +1100 (AEDT)","from localhost ([::1]:59930 helo=lists.gnu.org)\n\tby lists.gnu.org with esmtp (Exim 4.71) (envelope-from\n\t)\n\tid 1eYNn2-0008I1-5y\n\tfor incoming@patchwork.ozlabs.org; Sun, 07 Jan 2018 22:07:56 -0500","from eggs.gnu.org ([2001:4830:134:3::10]:51474)\n\tby lists.gnu.org with esmtp (Exim 4.71)\n\t(envelope-from )\n\tid 1eYNSj-00072r-MI\n\tfor qemu-devel@nongnu.org; Sun, 07 Jan 2018 21:46:58 -0500","from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)\n\t(envelope-from )\n\tid 1eYNSi-0002cc-RW\n\tfor qemu-devel@nongnu.org; Sun, 07 Jan 2018 21:46:57 -0500","from mail-qk0-x243.google.com ([2607:f8b0:400d:c09::243]:39182)\n\tby eggs.gnu.org with esmtps (TLS1.0:RSA_AES_128_CBC_SHA1:16)\n\t(Exim 4.71) (envelope-from )\n\tid 1eYNSi-0002c5-MZ\n\tfor qemu-devel@nongnu.org; Sun, 07 Jan 2018 21:46:56 -0500","by mail-qk0-x243.google.com with SMTP id r8so8244073qke.6\n\tfor ; Sun, 07 Jan 2018 18:46:56 -0800 (PST)","from x1.local ([138.117.48.219]) by smtp.gmail.com with ESMTPSA id\n\td10sm7156245qkg.16.2018.01.07.18.46.53\n\t(version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128);\n\tSun, 07 Jan 2018 18:46:55 -0800 (PST)"],"DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025;\n\th=sender:from:to:cc:subject:date:message-id:in-reply-to:references\n\t:mime-version:content-transfer-encoding;\n\tbh=pAgvLUCO+EF1HuNrh0zdqYdEE2+70gvpBwJ+DSvZcHM=;\n\tb=rMPM8bwnBSHInKV2N5femdmz+iyDtuAnihO7qmetDWtO1xDls97504n2NxS2KKluJv\n\t6vBY6sBDiRTUZIDhTt0B7FlPY+uG7g0tsdwWydbULmSGBvdkyWHJCjMKKkfjYLfmBR1j\n\tqHLN27IWNaJn0+1KaVSnEDvzu57SFJ2SEnMjrtPOWUFTYH7iLQerohXbdg63Ij1ROmbu\n\t71MGSVlq8AXFfRsEnpU5FSuuogeuZKgmpiUXVWlrsW1GOugIsgp1/oJUeRVXI/7WubC7\n\tCFCDakz8D5TGXDCed2jyHK7BvNFS/mbQGaVAEy64ny5HTN4AFwSvzFKuK5ZumAcgNnlL\n\tHxYg==","X-Google-DKIM-Signature":"v=1; a=rsa-sha256; c=relaxed/relaxed;\n\td=1e100.net; s=20161025;\n\th=x-gm-message-state:sender:from:to:cc:subject:date:message-id\n\t:in-reply-to:references:mime-version:content-transfer-encoding;\n\tbh=pAgvLUCO+EF1HuNrh0zdqYdEE2+70gvpBwJ+DSvZcHM=;\n\tb=pl6HU8RJZz4ycK6g8XByQpqzHBSnKJHBSMYXaClQ2Pr/UjtzzqF45bay68KCwf4zn6\n\tNZQvyjD4mK3WUuJcdRM2Q4uyDdmN/33v/Hnq2KJx9pW4CTeyofSbMrjXzCNMFtacpxPD\n\txruwL5n2dalenzndmuqq4ASbV0RmW697FPAnuoCPKB3vY9VeuVzPLIZozb1Sw+Q/Wp+L\n\tNlhpGz4GJZbfBQfh6BSfAM5/6F75slrxe9KU0AXCtKgWjEVXUPVIeyNpLDtjdb4/EKym\n\t3+KOwGi2CrFRbGOm+1zMlDb9G7JrMPBRnY+obSTGn53SoO5zD587vKy2PV8MxPhubBxn\n\t0eLQ==","X-Gm-Message-State":"AKwxytcU/5qHGBzFRVBHPovYNdp9Iy1QvasC3ffNto+zJpRsY8EX6+Qu\n\t9WO4jbSJbtpDBqIqpON3f6c=","X-Google-Smtp-Source":"ACJfBotpg6y4toE37J3MNHgYH1Mq+tr4titxDs8DuYQt++aShrg6o2mZuT3p2HF1zZC2Y2j615n/Bg==","X-Received":"by 10.55.209.137 with SMTP id o9mr11944830qkl.234.1515379616189; \n\tSun, 07 Jan 2018 18:46:56 -0800 (PST)","From":"=?utf-8?q?Philippe_Mathieu-Daud=C3=A9?= ","To":"Paolo Bonzini ,\n\t\"Michael S. Tsirkin\" , =?utf-8?q?Herv=C3=A9_Poussinea?=\n\t=?utf-8?q?u?= ,\n\tAurelien Jarno , Eduardo Habkost\n\t, Marcel Apfelbaum ","Date":"Sun, 7 Jan 2018 23:45:43 -0300","Message-Id":"<20180108024558.17983-15-f4bug@amsat.org>","X-Mailer":"git-send-email 2.15.1","In-Reply-To":"<20180108024558.17983-1-f4bug@amsat.org>","References":"<20180108024558.17983-1-f4bug@amsat.org>","MIME-Version":"1.0","Content-Type":"text/plain; charset=UTF-8","Content-Transfer-Encoding":"8bit","X-detected-operating-system":"by eggs.gnu.org: Genre and OS details not\n\trecognized.","X-Received-From":"2607:f8b0:400d:c09::243","Subject":"[Qemu-devel] [PATCH 14/29] piix4: add Reset Control Register","X-BeenThere":"qemu-devel@nongnu.org","X-Mailman-Version":"2.1.21","Precedence":"list","List-Id":"","List-Unsubscribe":",\n\t","List-Archive":"","List-Post":"","List-Help":"","List-Subscribe":",\n\t","Cc":"Igor Mammedov , qemu-devel@nongnu.org","Errors-To":"qemu-devel-bounces+incoming=patchwork.ozlabs.org@nongnu.org","Sender":"\"Qemu-devel\"\n\t"},"content":"From: Hervé Poussineau \n\nThe RCR I/O port (0xcf9) is used to generate a hard reset or a soft reset.\n\nAcked-by: Michael S. Tsirkin \nAcked-by: Paolo Bonzini \nSigned-off-by: Hervé Poussineau \n---\n hw/isa/piix4.c | 39 +++++++++++++++++++++++++++++++++++++++\n 1 file changed, 39 insertions(+)","diff":"diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c\nindex 314f7f7359..13f4eaa2dd 100644\n--- a/hw/isa/piix4.c\n+++ b/hw/isa/piix4.c\n@@ -2,6 +2,7 @@\n * QEMU PIIX4 PCI Bridge Emulation\n *\n * Copyright (c) 2006 Fabrice Bellard\n+ * Copyright (c) 2018 Hervé Poussineau\n *\n * Permission is hereby granted, free of charge, to any person obtaining a copy\n * of this software and associated documentation files (the \"Software\"), to deal\n@@ -33,6 +34,10 @@ PCIDevice *piix4_dev;\n \n typedef struct PIIX4State {\n PCIDevice dev;\n+\n+ /* Reset Control Register */\n+ MemoryRegion rcr_mem;\n+ uint8_t rcr;\n } PIIX4State;\n \n #define TYPE_PIIX4_PCI_DEVICE \"PIIX4\"\n@@ -87,6 +92,34 @@ static const VMStateDescription vmstate_piix4 = {\n }\n };\n \n+static void piix4_rcr_write(void *opaque, hwaddr addr, uint64_t val,\n+ unsigned int len)\n+{\n+ PIIX4State *s = opaque;\n+\n+ if (val & 4) {\n+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);\n+ return;\n+ }\n+ s->rcr = val & 2; /* keep System Reset type only */\n+}\n+\n+static uint64_t piix4_rcr_read(void *opaque, hwaddr addr, unsigned int len)\n+{\n+ PIIX4State *s = opaque;\n+ return s->rcr;\n+}\n+\n+static const MemoryRegionOps piix4_rcr_ops = {\n+ .read = piix4_rcr_read,\n+ .write = piix4_rcr_write,\n+ .endianness = DEVICE_LITTLE_ENDIAN,\n+ .impl = {\n+ .min_access_size = 1,\n+ .max_access_size = 1,\n+ },\n+};\n+\n static void piix4_realize(PCIDevice *pci_dev, Error **errp)\n {\n DeviceState *dev = DEVICE(pci_dev);\n@@ -96,6 +129,12 @@ static void piix4_realize(PCIDevice *pci_dev, Error **errp)\n pci_address_space_io(pci_dev), errp)) {\n return;\n }\n+\n+ memory_region_init_io(&s->rcr_mem, OBJECT(dev), &piix4_rcr_ops, s,\n+ \"reset-control\", 1);\n+ memory_region_add_subregion_overlap(pci_address_space_io(pci_dev), 0xcf9,\n+ &s->rcr_mem, 1);\n+\n piix4_dev = pci_dev;\n }\n \n","prefixes":["14/29"]}